CY22801_09 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – Universal Programmable Clock Generator

CY22801
Universal Programmable Clock Generator
(UPCG)
Features
■ Integrated Phase-Locked Loop (PLL)
■ Field Programmable
■ Input Frequency Range:
❐ Crystal: 8 to 30 MHz
❐ CLKIN: 1 to 133 MHz
■ LVCMOS Output Frequency:
❐ 1 to 200 MHz (Commercial Grade)
❐ 1 to 166.6 MHz (Industrial Grade)
■ Low Jitter, High Accuracy Outputs
■ 3.3V Operation
■ Commercial and Industrial Temperature Ranges
■ 8-Pin SOIC Package
Logic Block Diagram
XIN/CLKIN
XOUT
XTAL
OSC
Benefits
■ Inventory of only one device, CY22801, used in various
applications
■ In-house programming of sample and prototype quantities is
made available using the CY36800 InstaClock kit
■ Input and output frequencies are customized to suit your needs
■ High-performance PLL is tailored for multiple applications
■ Critical timing requirements met in complex system designs
■ Application compatibility enabled
PLL
OUTPUT
DIVIDERS
CLKA
CLKB
CLKC
Pin Configuration
Figure 1. CY22801 8-Pin SOIC
XIN/CLKIN 1
VDD ²
NC 3
VSS 4
8 XOUT
7 CLKC
6 CLKA
5 CLKB
Table 1. Pin Definition
Name
XIN
VDD
NC
VSS
CLKB
CLKA
CLKC
XOUT
Pin Number
1
2
3
4
5
6
7
8
Description
Reference Input: Crystal or External Clock
3.3V Voltage Supply
No Connect; leave this pin floating
Ground
Clock Output B
Clock Output A
Clock Output C
Reference Output: Connect to external crystal. When the reference is an external clock signal
(applied to pin 1), this pin is not used and must be left floating.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-15571 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 26, 2009
[+] Feedback