CY22800_07 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – Universal Programmable Clock Generator (UPCG)

Features
• Spread Spectrum, VCXO, and Frequency Select
• Input frequency range:
— Crystal: 8–30 MHz
— CLKIN: 0.5–100 MHz
• Output frequency:
— Commercial: 1–200 MHz
— Industrial: 1–166 MHz
• Integrated phase-locked loop
• Low jitter, high accuracy outputs
• 3.3V operation
• 8-pin SOIC package
Logic Block Diagram
CY22800
Universal Programmable Clock
Generator (UPCG)
Benefits
• Inventory of only one device, CY22800, is needed in various
applications such as HDTV, STB, DVDR, etc.
• Multiple predefined configurations that can be programmed
into a single chip
• Eliminates the need for expensive and difficult to use
higher-order crystal
• High-performance PLL tailored for multiple applications
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
• Allows up to three different frequency selects
Pin Configuration
XIN/CLKIN
XOUT
VCXO
OSC
FS2
FS1
FS0
Q_Φ
VCO
P
PLL
(with modulation control)
OUTPUT
DIVIDER
VDD VSS
CLKC
CLKB
CLKA
CY22800
8-pin SOIC
XIN/CLKIN 1
VDD 2
FS0/VCXO 3
VSS 4
8 XOUT
7 CLKC/FS2/VSS
6 CLKA/FS0
5 CLKB/FS1
Pin Description
Name
XIN
VDD
FS0/VCXO
VSS
CLKB/FS1
CLKA/FS0
CLKC/FS2/VSS
XOUT
Pin Number Description
1
Reference Input; Crystal or External Clock
2
3.3V Voltage Supply
3
Frequency Select 0/VCXO Analog Control Voltage^[1]
4
Ground
5
Clock Output B/Frequency Select 1^[1]
6
Clock Output A/Frequency Select 0^[1]
7
Clock Output C/Frequency Select 2/VSS^[1]
8
Reference Output (No Connect when the reference is a clock)
Note
1. Pin definition changes for different configurations. Refer to the specific one-page data sheet for more details.
Cypress Semiconductor Corporation
Document #: 001-07704 Rev. *A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised May 11, 2007
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