CY2277A Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 6x86, K6 Clock Synthesizer/Driver for Desktop Mobile PCs with Intel 82430TX and 2 DIMMs or 3 SO-DIMMs

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CY2277A
Pentium^®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/
Mobile PCs with Intel^® 82430TX and 2 DIMMs or 3 SO-DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution to meet requirements of Pen-
tium^®, Pentium^® II, 6x86, or K6 motherboards
— Four CPU clocks at 2.5V or 3.3V
— Up to eight 3.3V SDRAM clocks
— Seven 3.3V synchronous PCI clocks, one free
running
— Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable
by serial interface
— One 2.5V IOAPIC clock at 14.318 MHz
— Two 3.3V Ref. clocks at 14.318 MHz
• Factory-EPROM programmable CPU, PCI, and USB/IO
clock frequencies for custom configuration
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• MODE Enable pin for CPU_STOP and PCI_STOP
• SMBus serial configuration interface
• Available in space-saving 48-pin SSOP and TSSOP
packages.
Functional Description
The CY2277A is a Clock Synthesizer/Driver for Pentium, Pen-
tium II, 6X86, and K6 portable PCs designed with the Intel^®
82430TX or similar chipsets. There are three available options
as shown in the selector guide
The CY2277A has power-down, CPU stop and PCI stop pins
for power management control. The CPU stop and PCI stop
are controlled by the MODE pin. They are multiplexed with
SDRAM clock outputs, and are selected when the MODE pin
is driven LOW. Additionally, these inputs are synchronized
on-chip, enabling glitch-free transitions. When the
CPU_STOP input is asserted, the CPU outputs are driven
LOW. When the PCI_STOP input is asserted, the PCI outputs
(except the free-running PCI clock) are driven LOW. Finally,
when the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.
The CY2277A outputs are designed for low EMI emission.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2277A Selector Guide
Clock Outputs
-1/-1M -3
-12/
-12M/
-7M -12I
CPU (60, 66.6 MHz)
4
--
4
4
CPU (33.3, 66.6 MHz) --
4
--
--
CPU (SMBus select-
--
--
--
--
able)
PCI (CPU/2)
7^[1]
7^[1]
7^[1]
7^[1]
SDRAM
6/8
6/8
6/8
6/8
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up
to nine selectable frequencies. There are up to eight 3.3V
SDRAM clocks and seven PCI clocks, running at one half the
CPU clock frequency. One of the PCI clocks is free-running.
Additionally, the part outputs two 3.3V USB/IO clocks at 48
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,
USB, and IO clock frequencies are factory-EPROM program-
mable for easy customization with fast turnaround times.
USB/IO (48 or 24 MHz) 2
IOAPIC (14.318 MHz) 1
Ref (14.318 MHz)
2
CPU-PCI delay
1–6 ns
Note:
1. One free-running PCI clock.
2
1
2
1–6 ns
2
1
2
<1 ns
2
1
2
1–4 ns
Logic Block Diagram
XTALIN
14.318
MHz
XTALOUT
OSC.
CPU
PLL
STOP
LOGIC
SEL
MODE
PWR_DWN
SCLK
SDATA
EPROM
SYS
PLL
SERIAL
INTERFACE
CONTROL
LOGIC
/2
Delay
STOP
LOGIC
Divide and
Mux Logic
Pin Configuration
IOAPIC (14.318 MHz)
V_DDQ2
REF [0–1]
(14.318)
CPUCLK[0–3]
REF1
REF0
V_SS
XTALIN
XTALOUT
SSOP
Top View
1
48
2
47
3
46
4
45
5
44
AV_DD
PWR_SEL
V_DDQ2
IOAPIC
PWR_DWN
V_DDCPU
SDRAM[0–5]
MODE 6
V_{DDQ3 7}
PCICLK_F 8
PCICLK0 ₉
V_{SS 10}
43 V_SS
42 CPUCLK0
41 CPUCLK1
40
V_DDCPU
39 CPUCLK2
SDRAM6/CPU_STOP
PCICLK1 11
PCICLK2 12
PCICLK3 13
38 CPUCLK3
37 V_SS
36 SDRAM0
SDRAM7/PCI_STOP
PCICLK4 14
V_DDQ3 15
PCICLK5 16
35 SDRAM1
34
V_DDQ3
33 SDRAM2
V_SS 17
32 _SDRAM3
PCI[0–5]
PCICLK_F
SEL 18
SDATA 19
SCLK 20
31 V_SS
30 _SDRAM4
29 SDRAM5
V_DDQ3 21
USBCLK/IOCLK[0:1] _USBCLK/IOCLK 22
USBCLK/IOCLK 23
28
V_DDQ3
27 _{SDRAM6/CPU_STOP}
26 SDRAM7/PCI_STOP
V_SS 24
25 AV_DD
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07332 Rev. *A
Revised December 7, 2002