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CY22180 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – Very Low Jitter Field and Factory Programmable Clock Generator | |||
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PRELIMINARY
CY22180
Features
⢠Low period and cycle-to-cycle jitter
â Typical pk-pk period jitter: 60 ps
⢠Wide output frequency range
â Commercial temperature: 20â200 MHz
â Industrial temperature: 20â166 MHz
⢠Input frequency range
â External crystal: 10â30 MHz fundamental crystal
â External reference: 10â133 MHz clock
⢠Integrated phase-locked loop (PLL)
⢠Field programmable and factory programmed options
⢠Programmable crystal load capacitor tuning array
⢠3.3V operation
⢠Commercial and industrial temperature ranges
⢠Power down or output enable function
Very Low Jitter Field and Factory
Programmable Clock Generator
Benefits
⢠Internal PLL generates up to 200 MHz output. Can generate
custom frequencies from an external crystal or a driven
source.
⢠In-house programming of samples and prototype quantities
can be done using the CY3672-USB programmer and
CY3619 socket adapter. Production quantities are available
through Cypressâs value added distribution partners or by
using third party programmers from BP Microsystems, HiLo
Systems, and others.
⢠Eliminates the need for expensive and difficult to use
higher-order crystals.
⢠Enables fine-tuning of output clock frequency by adjusting
CLoad of the crystal. Eliminates the need for external CLoad
capacitors.
⢠Application compatibility in standard and low-power
systems
⢠Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
1
XIN/CLKIN
8
XOUT
3
PD# or OE
CXIN
CXOUT
PLL
PROGRAMMABLE
CONFIGURATION
2
VDD
4
VSS
OUTPUT
DIVIDER
6
CLKOUT
5
REFOUT
Pin Configuration
CY22180
8-pin SOIC
1 XIN/CLKIN
XOUT 8
2 VDD
NC 7
3 PD#/OE
CLKOUT 6
4 VSS
REFOUT 5
Cypress Semiconductor Corporation
Document #: 001-15577 Rev. **
⢠198 Champion Court ⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised May 10, 2007
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