CY2210 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support

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CY2210
133-MHz Spread Spectrum Clock Synthesizer/Driver
with AGP, USB, and DRCG Support
Features
• Mixed 2.5V and 3.3V Operation
• Compliant to Intel^® CK133 (CY2210-3) & CK133W
(CY2210-2) synthesizer and driver specification
• Multiple output clocks at different frequencies
— Four CPU clocks, up to 133 MHz
— Eight synchronous PCI clocks, 1 free-running
— Two CPU/2 clocks, at one-half the CPU frequency
— Four AGP clocks at 66 MHz
— Three synchronous APIC clocks, at 16.67 MHz
— One USB clock at 48 MHz
— Two reference clocks at 14.318 MHz
• Spread Spectrum clocking
— 32.5-kHz modulation frequency @ 133 MHz
— 33.1-kHz modulation frequency @ 100 MHz for
CY2210-02/03
— 33.4-kHz modulation frequency @ 100 MHz for
CY2210-04
— EPROM programmable percentage of spreading.
Default is –0.6%, which is recommended by Intel
• Power-down features
• Three Select inputs
• Low-skew and low-jitter outputs
• OE and Test Mode support
• 56-pin SSOP package
Benefits
Usable with Pentium^® II and Pentium^® III processors
Single-chip main motherboard clock generator
— Driven together, support 4 CPUs and a chipset
— Support for 4 PCI slots and chipset
— Drives up to two main memory clock generators, includ-
ing DRCG (CPUCLK/2)
— Support for multiple AGP slots
— Support multiprocessing systems
— Supports USB frequencies and I/O chip
Enables reduction of EMI in some systems
Supports mobile systems
Supports up to eight CPU clock frequencies
Meets tight system timing requirements at high frequency
Enables ATE and “bed of nails” testing
Widely available, standard package enables lower cost
Logic Block Diagram
CPU_STOP
XTALIN
XTALOUT
14.318
MHz
OSC.
SEL1
SEL0
SEL133
SPREAD
PCI_STOP
PWR_DWN
CPU
PLL
EPROM
SYS
PLL
Divider,
EPROM-
ProgDelay
and
Stop Logic
Intel and Pentium are registered trademarks of Intel Corporation.
Pin Configuration
SSOP
Top View
REFCLK [0–1] (14.318 MHz) V_SSREF 1
56
REFCLK0 2
55
REFCLK1 3
54
CPUCLK [0–3]
V_DDREF
4
53
XTALIN 5
52
XTALOUT 6
51
V_SSPCI
7
50
CPUCLK/2 [0–1] (DRCG)
PCICLK_F ₈
49
PCICLK1 ₉
48
PCICLK_F (33.33 MHz)
V_DDPCI
10
47
PCICLK2 ₁₁
46
PCICLK3 ₁₂
45
PCICLK [1–7] (33.33 MHz)
V_SSPCI
13
44
PCICLK4 14
43
APICCLK [0–2] (16.67 MHz) _{PCICLK5 15}
42
V_DDPCI
16
41
AGPCLK [0–3] (66.67 MHz) _PCICLK6 17
40
PCICLK7 18
39
USBCLK (48 MHz)
V_SSPCI
19
38
V_SSAGP
20
37
AGPCLK0 ₂₁
36
AGPCLK1 22
35
V_DDAGP
23
34
V_SSAGP
24
33
AGPCLK2 25
32
AGPCLK3 ₂₆
31
V_DDAGP
27
30
SEL133 ₂₈
29
V_DDAPIC
APICCLK2
APICCLK1
APICCLK0
V_SSAPIC
V_DDCPU/2
CPUCLK/2
(DRCG)
CPUCLK/2
(DRCG)
V_SSCPU/2
V_DDCPU
CPUCLK3
CPUCLK2
V_SSCPU
V_DDCPU
CPUCLK1
CPUCLK0
V_SSCPU
AV_DD
AV_SS
PCI_STOP
CPU_STOP
PWR_DWN
SPREAD
SEL1
SEL0
V_DDUSB
USBCLK
V_SSUSB
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07204 Rev. *A
Revised December 14, 2002