CY2048WAF Datasheet, PDF (1/7 Pages) Cypress Semiconductor – Flash Programmable Capacitor Tuning Array Die for Crystal Oscillator(XO)

CY2048WAF
Flash Programmable Capacitor Tuning Array Die
for Crystal Oscillator(XO)
Features
• Flash-programmable capacitor tuning array for low
ppm initial frequency clock output
• Low clock output jitter
— 4 ps typ. RMS period jitter
— ±30 ps typ. peak-to-peak period jitter
• Flash-programmable dividers
• Two-pin programming interface
• On-chip oscillator runs from 10–48-MHz crystal
• Five selectable post-divide options, using reference
oscillator output
• Programmable asynchronous or synchronous OE and
PWR_DWN modes
• 2.7V to 3.6V operation
• Controlled rise and fall times and output slew rate
Block Diagram
PD#/OE
(SDATA/VPP)
Benefits
• Enables fine-tuning of output clock frequency by
adjusting C_Load of the crystal
• Allows multiple programming opportunities to correct
errors, and control excess inventory
• Enables programming of output frequency after
packaging
• PPM clock output error can be adjusted in package
• Provides flexibility in output configurations and testing
• Enables low-power operation or output enable function
• Provides flexibility for system applications through
selectable instantaneous or synchronous change in
outputs
• Enables encapsulation in small-size, surface-mount
packages
XIN
XOUT
CRYSTAL
OSCILLATOR
CONFIGURATION
Die Pad Description
H orizontal Scribe
1 VDD
2 _XOUT
Y (m ax)
OUT 6
3 X IN
4 P D #/O E
7C80330A
VSS ⁵
V ertical
S c rib e
d ie # /re v
X(m ax)
/ 1, 2, 4, 8, 16
VDD
VSS
OUT
(SCL)
Notes:
X(max): 980 µm, Y(max): 988 µm
Scribe: X = 70 µm, Y = 86 µm
Bond pad opening: 85 µm x 85 µm
Pad pitch: 175 µm (min.)
Wafer thickness: 11 mils (Typ.)
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07738 Rev. *A
Revised December 12, 2005