CY14V104LA Datasheet, PDF (1/22 Pages) Cypress Semiconductor – 4-Mbit (512 K x 8 / 256 K x 16) nvSRAM 25 ns and 45 ns access times

CY14V104LA
CY14V104NA
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
Features
Functional Description
■ 25 ns and 45 ns access times
■ Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16
(CY14V104NA)
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and recall cycles
■ 1-million STORE cycles to QuantumTrap
The Cypress CY14V104LA/CY14V104NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
organized as 512 K bytes of 8 bits each or 256 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
■ 20 year data retention
■ Core V_CC = 3.0 V to 3.6 V; IO V_CCQ = 1.65 V to 1.95 V
■ Industrial temperature
■ 48-ball fine-pitch ball grid array (FBGA) package
■ Pb-free and restriction of hazardous substances (RoHS)
compliance
Logic Block Diagram ^{[1, 2, 3]}
Quatrum Trap
V_CC V_CCQ V_CAP
2048 X 2048
A₀
R
POWER
A₁
O
STORE
CONTROL
A₂
A₃
A₄
A₅
W
RECALL
D
E
STATIC RAM
STORE/RECALL
CONTROL
HSB
A₆
C
ARRAY
A₇
A₈
A ₁₇
O
2048 X 2048
D
E
SOFTWARE
DETECT
A₁₄ - A₂
A₁₈
R
DQ₀
DQ ₁
DQ ₂
DQ ₃
DQ₄
DQ₅
DQ ₆
DQ ₇
DQ₈
DQ ₉
DQ ₁₀
DQ ₁₁
DQ ₁₂
DQ ₁₃
DQ ₁₄
DQ ₁₅
I
N
P
U
T
B
COLUMN I/O
U
F
F
E
R
COLUMN DEC
S
A₉ A₁₀ A₁₁ A₁₂ A₁₃ A₁₄ A₁₅ A₁₆
OE
WE
CE
BLE
BHE
Notes
1. Address A₀–A₁₈ for × 8 configuration and Address A₀–A₁₇ for × 16 configuration.
2. Data DQ₀–DQ₇ for × 8 configuration and Data DQ₀–DQ₁₅ for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-53954 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 6, 2011
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