CY14V101LA Datasheet, PDF (1/22 Pages) Cypress Semiconductor – 1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles

CY14V101LA
CY14V101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
1-Mbit (128 K × 8/64 K × 16) nvSRAM
Features
■ 25 ns and 45 ns access times
■ Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16
(CY14V101NA)
■ Hands off automatic STORE on power down with only a small
capacitor
■ STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power down
■ RECALL to SRAM initiated by software or power up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Core V_CC = 3.0 V to 3.6 V; I/O V_CCQ = 1.65 V to 1.95 V
■ Industrial temperature
■ 48-ball fine-pitch ball grid array (FBGA) package
■ Pb-free and restriction of hazardous substances (RoHS)
compliance
Functional Description
The Cypress CY14V101LA/CY14V101NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
organized as 128 K bytes of 8 bits each or 64 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
Logic Block Diagram ^{[1, 2, 3]}
A₅
R
O
A₆
W
A₇
A₈
D
A₉
E
A₁₂
C
A₁₃
O
A₁₄
D
A₁₅
E
A₁₆
R
DQ₀
DQ₁
DQ₂
DQ₃
DQ₄
I
N
DQ₅
P
DQ₆
U
T
DQ₇
B
DQ₈
U
F
DQ₉
F
DQ₁₀
E
R
DQ₁₁
S
DQ₁₂
DQ₁₃
DQ₁₄
DQ₁₅
Quatrum Trap
1024 X 1024
STORE
RECALL
STATIC RAM
ARRAY
1024 X 1024
COLUMN I/O
COLUMN DEC
A₀ A₁ A₂ A₃ A₄ A₁₀ A₁₁
V_CC VCCQ V_CAP
POWER
CONTROL
STORE/RECALL
CONTROL
SOFTWARE
DETECT
HSB
A₁₄ - A₂
OE
WE
CE
BLE
BHE
Notes
1. Address A₀–A₁₆ for × 8 configuration and Address A₀–A₁₅ for × 16 configuration.
2. Data DQ₀–DQ₇ for × 8 configuration and Data DQ₀–DQ₁₅ for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-53953 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 4, 2011
[+] Feedback