CY14B256L Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 256-Kbit (32K x 8) nvSRAM

PRELIMINARY
CY14B256L
256-Kbit (32K x 8) nvSRAM
Features
• 25 ns, 35 ns, and 45 ns access times
• “Hands-off” automatic STORE on power down with only a
small capacitor
• STORE to QuantumTrap™ nonvolatile elements is initiated
by software, device pin, or AutoStore™ on power down
• RECALL to SRAM initiated by software or power up
• Infinite READ, WRITE, and RECALL cycles
• 10 mA typical I_CC at 200 ns cycle time
• 200,000 STORE cycles to QuantumTrap
• 20-year data retention @ 55°C
• Single 3V operation with tolerance of +15%, –10%
• Commercial and industrial temperature
• SOIC and SSOP packages
• RoHS compliance
Logic Block Diagram
Functional Description
The Cypress CY14B256L is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
infinite read and write cycles while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. The STORE and
RECALL operations are also available under software control.
QuantumTrap
V_CC
V_CAP
512 X 512
A₅
STORE
POWER
CONTROL
A₆
A₇
A₈
STATIC RAM
RECALL
STORE/
A₉
ARRAY
A ₁₁
A ₁₂
512 X 512
RECALL
CONTROL
HSB
A ₁₃
A ₁₄
SOFTWARE
DETECT
- A₁₃ A₀
DQ ₀
DQ ₁
DQ ₂
DQ ₃
DQ ₄
DQ ₅
DQ ₆
DQ ₇
COLUMN IO
COLUMN DEC
A₀ A₁ A₂ A₃ A₄ A₁₀
OE
CE
WE
Cypress Semiconductor Corporation
Document #: 001-06422 Rev. *E
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised January 27, 2007
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