CY14B104LA_11 Datasheet, PDF (1/24 Pages) Cypress Semiconductor – 4-Mbit (512 K × 8/256 K × 16) nvSRAM

CY14B104LA, CY14B104NA
4-Mbit (512 K × 8/256 K × 16) nvSRAM
Features
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 512 K × 8 (CY14B104LA) or 256 K ×
16 (CY14B104NA)
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20%, -10% operation
■ Industrial temperature
■ Packages
❐ 44-/54-pin thin small outline package (TSOP II)
❐ 48-ball fine-pitch ball grid array (FBGA)
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B104LA/CY14B104NA is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 512 K bytes of 8 bits each or 256 K
words of 16 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
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Notes
1. Address A₀ - A₁₈ for ×8 configuration and Address A₀ - A₁₇ for ×16 configuration.
2. Data DQ₀ - DQ₇ for ×8 configuration and Data DQ₀ - DQ₁₅ for ×16 configuration.
3. BHE and BLE are applicable for ×16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-49918 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 18, 2011
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