B9949 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 3.3V 160-MHz 1:15 Clock Distribution Buffer

B9949
3.3V 160-MHz 1:15 Clock Distribution Buffer
Features
• 160MHz Clock Support
• LVPECL or LVCMOS/LVTTL Clock Input
• LVCMOS/LVTTL Compatible Inputs
• 15 Clock Outputs: Drive up to 30 Clock Lines
• 1X and 1/2X Configurable Outputs
• Output Three-state Control
• 350 ps Maximum Output-to-Output Skew
• Pin Compatible with MPC949
• Industrial Temp. Range: –40°C to +85°C
• 52-Pin TQFP Package
Block Diagram
TCLK_SEL
TCLK0 (LVTTL) 0
0
TCLK1 (LVTTL) ₁
1
PECL_CLK
PECL_CLK#
PCLK_SEL
DSELA
DSELB
DSELC
DSELD
MR/OE#
Description
The B9949 is a low-voltage clock distribution buffer with the
capability to select either a differential LVPECL or LVC-
MOS/LVTTL compatible input clocks. These clock sources
can be used to provide for test clocks as well as the primary
system clocks. All other control inputs are LVCMOS/LVTTL
compatible. The 15 outputs are 3.3V LVCMOS or LVTTL com-
patible and can drive two series terminated 50Ω transmission
lines. With this capability the B9949 has an effective fan-out of
1:30.
The B9949 is capable of generating 1X and 1/2X signals from
a 1X source. These signals are generated and retimed inter-
nally to ensure minimal skew between the 1X and 1/2X sig-
nals. SEL(A:D) inputs allow flexibility in selecting the ratio of
1X to1/2X outputs.
The B9949 outputs can also be three-stated via MR/OE# in-
put. When MR/OE# is set HIGH, it resets the internal flip-flops
and three-states the outputs.
/1
/2
R
0
1
0
1
0
1
0
1
2 _QA0:1
3 _QB0:2
4
QC0:3
6 _QD0:5
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07081 Rev. *C
Revised December 21, 2002