B9948L Datasheet, PDF (1/6 Pages) Cypress Semiconductor – 2.5V/3.3V, 160-MHz, 1:12 Clock Distribution Buffer

B9948L
2.5V/3.3V, 160-MHz, 1:12 Clock Distribution Buffer
Product Features
• 160-MHz clock support
• 2.5V or 3.3V output capability
• 200-ps maximum output-to-output skew
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL compatible inputs
• 12 clock outputs: drive up to 24 clock lines
• Synchronous Output Enable
• Output Three-state control
• Pin compatible with MPC948L
• Industrial temp. range: –40°C to +85°C
• 32-pin TQFP package
Block Diagram
Description
The B9948L is a low-voltage clock distribution buffer with the
capability to select either a differential LVPECL or a LVCMOS/
LVTTL compatible input clock. The two clock sources can be
used to provide for a test clock as well as the primary system
clock. All other control inputs are LVCMOS/LVTTL compatible.
The twelve outputs are 2.5V or 3.3V LVCMOS or LVTTL com-
patible and can drive two series-terminated 50Ω transmission
lines. With this capability the B9948L has an effective fanout
of 1:24. The outputs can also be three-stated via the three-
state input TS#. Low output-to-output skews make the B9948L
an ideal clock distribution buffer for nested clock trees in the
most demanding of synchronous systems.
The B9948L also provides a synchronous output enable input
for enabling or disabling the output clocks. Since this input is
internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Pin Configuration
PECL_CLK
PECL_CLK#
TCLK
TCLK_SEL
SYNC_OE
TS#
VDD
0
1
VDDC
12 _Q0-Q11
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
1
24 VSS
2
23 Q4
3
22 VDDC
B9948L ⁴
21 Q5
5
20 VSS
6
19 Q6
7
18 VDDC
8
17 Q7
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07080 Rev. *C
Revised December 21, 2002