B9948 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – 3.3V, 160-MHz, 1:12 Clock Distribution Buffer

B9948
3.3V, 160-MHz, 1:12 Clock Distribution Buffer
Features
Description
• 160-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL compatible inputs
• 12 clock outputs: drive up to 24 clock lines
• Synchronous Output Enable
• Output three-state control
• 350-ps maximum output-to-output skew
• Pin compatible with MPC948
• Industrial temp. range: –40°C to +85°C
• 32-pin TQFP package
Block Diagram
The B9948 is a low-voltage clock distribution buffer with the
capability to select either a differential LVPECL or a LVC-
MOS/LVTTL compatible input clock. The two clock sources
can be used to provide for a test clock as well as the primary
system clock. All other control inputs are LVCMOS/LVTTL
compatible. The twelve outputs are 3.3V LVCMOS or LVTTL
compatible and can drive two series terminated 50Ω transmis-
sion lines. With this capability the B9948 has an effective
fan-out of 1:24. The outputs can also be three-stated via the
three-state input TS#. Low output-to-output skews make the
B9948 an ideal clock distribution buffer for nested clock trees
in the most demanding of synchronous systems.
The B9948 also provides a synchronous output enable input
for enabling or disabling the output clocks. Since this input is
internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Pin Configuration
PECL_CLK
PECL_CLK#
TCLK
TCLK_SEL
SYNC_OE
TS#
VDD
0
1
VDDC
12 _Q0-Q11
TCLK_SEL 1
TCLK 2
PECL_CLK 3
PECL_CLK# 4
SYNC_OE 5
TS# 6
VDD 7
VSS 8
B9948
24 VSS
23 Q4
22 VDDC
21 Q5
20 VSS
19 Q6
18 VDDC
17 Q7
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07079 Rev. *D
Revised December 14, 2002