B9946 Datasheet, PDF (1/5 Pages) Cypress Semiconductor – 3.3V, 160-MHz, 1:10 Clock Distribution Buffer

B9946
3.3V, 160-MHz, 1:10 Clock Distribution Buffer
Product Features
• 160-MHz Clock Support
• LVCMOS/LVTTL Compatible Inputs
• 10 Clock Outputs: Drive up to 20 Clock Lines
• 1X or 1/2X Configurable Outputs
• Output Three-state Control
• 250 ps Maximum Output-to-Output Skew
• Pin Compatible with MPC946
• Industrial Temp. Range: –40°C to +85°C
• 32-Pin TQFP Package
Block Diagram
Description
The B9946 is a low-voltage clock distribution buffer with the
capability to select one of two LVCMOS/LVTTL compatible in-
put clocks. These clock sources can be used to provide for test
clocks as well as the primary system clocks. All other control
inputs are LVCMOS/LVTTL compatible. The 10 outputs are
3.3V LVCMOS or LVTTL compatible and can drive two series
terminated 50Ω transmission lines. With this capability the
B9946 has an effective fanout of 1:20.
The B9946 is capable of generating 1X and 1/2X signals from
a 1X source. These signals are generated and retimed inter-
nally to ensure minimal skew between the 1X and 1/2X sig-
nals. SEL(A:C) inputs allow flexibility in selecting the ratio of
1X to1/2X outputs.
The B9946 outputs can also be three-stated via MR/OE# in-
put. When MR/OE# is set HIGH, it resets the internal flip-flops
and three-states the outputs.
Pin Configuration
TCLK_SEL
TCLK0
0
TCLK1
1
DSELA
DSELB
DSELC
/1
/2
R
0
1
0
1
0
1
3 _QA0:2
3 _QB0:2
4
QC0:3
TCLK_SEL 1
VDD 2
TCLK0 3
TCLK1 4
DSELA 5
DSELB 6
DSELC 7
VSS 8
B9946
24 VSS
23 QB0
22 VDDC
21 QB1
20 VSS
19 QB2
18 VDDC
17 VDDC
MR/OE#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07077 Rev. *C
Revised December 22, 2002