PYB20-T Datasheet, PDF (7/8 Pages) CUI INC – DC-DC CONVERTER

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CUI Inc │ SERIES: PYB20-T & PYB20-U │ DESCRIPTION: DC-DC CONVERTER
date 06/16/2015 │ page 7 of 8
APPLICATION NOTES
1. Recommended circuit
This series has been tested according to the following recommended testing circuit before leaving the factory. This series should be
tested under load (see Figure 2). If you want to further decrease the input/output ripple, you can increase the capacitance accord-
ingly or choose capacitors with low ESR (see Table 2). However, the capacitance of the output filter capacitor must be appropriate. If
the capacitance is too high, a startup problem might arise. For every channel of the output, to ensure safe and reliable operation, the
maximum capacitance must be less than the maximum capacitive load (see Table 3).
Single Output
Vi n
Cin
GND
DC DC ^Cout
Figure 2
Dual Output
+Vo
Vi n
Cout
+Vo
Cin
DC DC
0V
0V
GND
Cout
-Vo
Table 2
Single Vout Cin
(Vdc)
(µF)
Cout Dual Vout
(µF)
(Vdc)
3.3
100 470
5
100 470
12
100 220
15
100 220
24
100 100
Note:
1. For each output.
--
±5
±12
±15
--
Cin
(µF)
--
100
100
100
--
Cout¹
(µF)
--
220
100
100
--
Table 3
Single Vout Max. Capacitive Load Dual Vout Max. Capacitive Load¹
(Vdc)
(μF)
(Vdc)
(μF)
3.3
10200
--
--
5
4020
5
4800
12
1035
12
800
15
705
15
24
470
--
Note:
1. For each output.
500
--
2. Output voltage trimming
Leave open if not used.
Figure 3
Application Circuit for Trim pin
(part in broken line is the interior of models)
Formula for Trim Resistor
+Vo
+ Vo
R1
Vre f ^R3
Trim
R1
Vref ^R3
RT
Trim
^{R2 RT} _R2


0 V ^0V
Tr im up
Tr im down
up: RT=
aR 2
R2-a
-R3
down : RT=
aR 1
R1-a
-R3
Vref
a =_{Vo’ - Vref} R1
a =^{Vo’ - Vref}
Vref
R2
Note:
Value for R1, R2, R3, and Vref refer to Table 4
R_T: Trim Resistor
a: User-defined parameter, no actual meanings
Vo': The trim up/down voltage
Table 4
Vout
(Vdc)
3.3
5
12
15
24
R1
(kΩ)
4.801
2.883
10.971
14.497
24.872
R2
(kΩ)
2.863
2.864
2.864
2.864
2.863
R3
(kΩ)
15
10
17.8
17.8
20
Vref
(V)
1.24
2.5
2.5
2.5
2.5
Note:
1. Minimum load shouldn't be less than 5%, otherwise ripple may increase dramatically. Operation under minimum load will not damage the converter, however, they may
not meet all specifications listed.
2. Maximum capacitive load is tested at input voltage range and full load.
3. All specifications are measured at Ta=25°C, humidity<75%, nominal input voltage and rated output load unless otherwise specified.
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