CY7C1069DV33_07 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 16-Mbit (2M x 8) Static RAM

CY7C1069DV33
16-Mbit (2M x 8) Static RAM
Features
■ High speed
❐ t_AA = 10 ns
■ Low active power
❐ I_CC = 175 mA at 10 ns
■ Low CMOS standby power
❐ I_SB2 = 25 mA
■ Operating voltages of 3.3 ± 0.3V
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE₁ and CE₂ features
■ Available in Pb-free 54-Pin TSOP II and 48-Ball VFBGA
packages
Logic Block Diagram
Functional Description
The CY7C1069DV33 is a high performance CMOS Static RAM
organized as 2,097,152 words by 8 bits.
To write to the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. Data on the eight IO
pins (IO₀ through IO₇) is then written into the location specified
on the address pins (A₀ through A₂₀).
To read from the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on the
IO pins. See Truth Table on page 8 for a complete description of
Read and Write modes.
The input and output pins (IO₀ through IO₇) are placed in a high
impedance state when the device is deselected (CE₁ HIGH or
CE₂ LOW), the outputs are disabled (OE HIGH), or during a write
operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
The CY7C1069DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-Ball very fine pitch ball grid array (VFBGA) package.
INPUT BUFFER
A₀
A₁
A₂
A₃
A₄
A₅
2M x 8
ARRAY
A₆
A₇
A₈
A₉
COLUMN
DECODER
IO₀ – IO₇
WE
CE₂
OE
CE₁
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05478 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 06, 2007