CCLD-054X-20-622.080 Datasheet, PDF (3/3 Pages) Crystek Corporation – LVDS Clock Oscillator

CCLD-054X-20-622.080
LVDS Clock Oscillator
0.274 ±0.007
(6.96 ±0.18)
CCLD054X20
622.08M
DC Lot Code
0.193 ±0.007
(4.90 ±0.18)
0.045 ±0.008
(1.14 ±0.20)
SUGGESTED PAD LAYOUT
Denotes pad 1
0.055 Typ
via to
ground
(1.40 Typ)
0.01µF
0.045 ±0.008
6
(1.14 ±0.20)
#1
#2
#3
#6
#5
#4
0.071
1
(1.80)
0.050
(1.27)
5
4
0.154
(3.91)
2
3
0.100
(2.54)
0.200
(5.08)
0.100
(2.54)
0.200
(5.08)
Pad Connection
1 Enable/Disable
2 N/C
3 GND
4 Out
5 Comp. Out
6 VCC
OUT
OUT
LVDS Test Circuit
50ȍ
VOD
VOS
50ȍ
RECOMMENDED REFLOW SOLDERING PROFILE
260°C
217°C
Ramp-Up
3°C/Sec Max.
Critical
Temperature Zone
Ramp-Down
6°C/Sec.
200°C
150°C
Preheat
180 Secs. Max.
8 Minutes Max.
90 Secs. Max.
260°C for
10 Secs. Max.
NOTE: Reflow Profile with 240°C peak also acceptable.
Rev.: B
Date: 10-10-07