CCLD-034_15 Datasheet, PDF (2/3 Pages) Crystek Corporation – LVDS Clock Oscillator

CCLD-034 Model
5×7 mm SMD, 3.3V, LVDS
CCLD-034 5×7mm SMD
LVDS Clock Oscillator
Frequency Range:
Frequency Stability Options(ppm):
Temperature Range:
(Option M)
(Option X)
Storage:
Input Voltage:
Input Current:
Output:
Symmetry:
Rise/Fall Time:
Load:
Logic:
Output Voltage Levels
Differential Output Voltage:
Disable Time:
Enable Time:
Phase Jitter: 12kHz~80MHz
Phase Noise: (See Plot Below)
Sub-harmonics:
Aging:
162.000 MHz to 250.000 MHz
±20, ±25, ±50, ±100
(standard) 0°C to +70°C
-20°C to +70°C
-40°C to +85°C
-45°C to 90°C
3.3V ±0.3V
45mA Typical, 66mA Max
Differential LVDS
45/55% Max @ zero crossing point
1nSec Max (20% to 80%)
100 Ohms Connected between OUT and COUT
“0”=0.90 Min, 1.10 Typical
“1”=1.43 Typical, 1.60 Max
247mV Min, 454mV Max
200nSec Max
2mSec Max
0.5pSec Typical, 1pSec RMS Max
None
<3ppm 1^st year, <1ppm every year thereafter
Actual CCLD-034-50-250.000 Plot
CRYSTEK
CORPORATION
Rev: M
Date: 16-Oct-2015
Page 2 of 3
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: [phone] • 800-237-3061
Fax: [phone] • www.crystek.com