CCHD-950 Datasheet, PDF (2/2 Pages) List of Unclassifed Manufacturers – Ultra-Low Phase Noise Clock Oscillator 9X14 mm SMD, 3.3V, CMOS

Frequency Range:
Temperature Range:

(Option M)

(Option X)
Storage:
Input Voltage:
Input Current:
Output:
Symmetry:
Rise/Fall Time:
Logic:

Load:
Output Current:
Jitter: 12KHz~80MHz
Phase Noise Floor:
Sub-harmonics:
Aging:
CCHD/CVHD-950
Ultra-Low Phase Noise
50Mhz to 125Mhz
0°C to +70°C
-20°C to +70°C
-40°C to +85°C
-55°C to 90°C
3.3V ± 0.3V
15mA Typ., 25mA Max
CMOS
45/55% Max @ 50%Vdd
3nsec Max @ 20% to 80% Vdd
“0” = 10% Vdd Max
“1” = 90% Vdd Min.
15pF
±24mA Max
0.5psec Typ., 1psec RMS Max
-160dBc Typ., -155dBc Max
None
<3ppm 1st/yr, <1ppm thereafter
Oscillators
Phase Noise Typ.:
1KHz
-131 dBc/Hz
10KHz
-155 dBc/Hz
100KHz -160 dBc/Hz
1MHz
-162 dBc/Hz
CCHD-950 Options Temperature Range: 0°C to +70°C (±20ppm, ±25ppm, ±50ppm)

-20°C to +70°C (±25ppm, ±50ppm)

-40°C to +85°C (±25ppm, ±50ppm)
CVHD-950
Frequency Pulling:
±20ppm APR Min.


Control Voltage:
Linearity:
1.65V ± 1.65V
±10% Max
Pad Connection
1 NC or Volt.
Part Number Example
CCHD-950X-25-100.000 = 3.3V, 45/55, -40°C to +85°C (±25ppm), 100MHz
CVHD-950X-100.000 = 3.3V, 45/55, -40°C to +85°C (±20ppmAPR), 100MHz
Cntrl.
2 GND
3 Output
4 Vdd
Rev.: C
Date: 12-9-05