DP7419 Datasheet, PDF (1/16 Pages) Copal Electronics – Dual Digital Potentiometers

DP7419
Dual Digital Potentiometers (DP)
with 64 Taps and 2-wire Interface
FEATURES
Two linear-taper digital potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kŸ, 10kŸ, 50kŸ or
100kŸ
Potentiometer control and memory access via
2-wire Interface (I²C like)
Low wiper resistance, typically 80
Four non-volatile wiper settings for each
potentiometer
Recall of wiper settings at power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Write protection for data register
DESCRIPTION
The DP7419 is two Digital Potentiometers (DPs)
integrated with control logic and 16 bytes of
NVRAM memory.
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DP.
Associated with each wiper control register are four 6-
bit non-volatile memory data registers (DR) used for
storing up to four wiper settings. Writing to the wiper
control register or any of the non-volatile data regis-
ters is via a 2-wire serial bus (I²C-like). On power-up,
the contents of the first data register (DR0) for each of
the two potentiometers is automatically loaded into its
respective wiper control registers (WCR).
The Write Protection (¯W¯P¯) pin protects against
inadvertent programming of the data register.
The DP7419 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC (W)
(top view)
V_CC 1
24 NC
R_L0 2
23 NC
R_H0 3
22 NC
R_W0 4
21 NC
A2 5
20 A₀
¯W¯P¯ 6 _CAT 19 NC
SDA 7 ⁵⁴¹⁹ 18 A₃
A₁ 8
17 SCL
R_L1 9
16 NC
R_H1 10
15 NC
R_W1 11
14 NC
GND 12
13 NC
TSSOP (Y)
(top view)
SDA 1
24 ¯W¯P¯
A₁ 2
23 A₂
R_L1 3
22 R_W0
R_H1 4
21 R_H0
R_W1 5
20 R_L0
GND 6 _CAT 19 V_CC
NC 7 ⁵⁴¹⁹ 18 NC
NC 8
17 NC
NC 9
16 NC
NC 10
15 NC
SCL 11
14 A₀
A₃ 12
13 NC
For Ordering Information details, see page 15.
FUNCTIONAL DIAGRAM
R_H0 R_H1
SCL
SDA
WP
A0
A1
A2
A3
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R_W0
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R_W1
R_L0 R_L1
© NIDEC COPAL ELECTRONICS CORP.
1
Characteristics subject to change without notice
Doc. No. MD-2115 Rev. H