DP7401 Datasheet, PDF (1/15 Pages) Copal Electronics – Quad Digital Potentiometers

Quad Digital Potentiometers
(DP) with 64 Taps and SPI Interface
DP7401
FEATURES
Four linear taper digital potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kŸ, 10kŸ, 50kŸ or
100kŸ
Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
Low wiper resistance, typically 80Ÿ
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Industrial temperature range
For Ordering Information details, see page 14.
DESCRIPTION
The DP7401 is four Digital Potentiometers
(DPs) integrated with control logic and 16 bytes
of NVRAM memory. Each DP consists of a series
of 63 resistive elements connected between
two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The DP7401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (W)
TSSOP Package (Y)
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1
24
2
23
3
22
4
21
5
20
6 _DP 19
7 ⁷⁴⁰¹ 18
8
17
9
16
10
15
11
14
12
13
NC
SI
RL3
A1
RH3 RL1
RW3 RH1
A0 RW1
SO GND
HOLD NC
SCK RW2
RL2 RH2
RH2 RL2
RW2 SCK
NC HOLD
1
24
2
23
3
22
4
21
5
20
6 _DP 19
7 ⁷⁴⁰¹ 18
8
17
9
16
10
15
11
14
12
13
WP
CS
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
SO
FUNCTIONAL DIAGRAM
CS
SCK
SI
SO
WP
A₀
A₁
R_H0
R_H1
R_H2
R_H3
SPI BUS
WIPER CONTROL
INTERFACE
REGISTERS
R_W0
R_W1
NONVOLATILE
R_W2
CONTROL LOGIC
DATA
REGISTERS
R_W3
R_L0
R_L1
R_L2
R_L3
© NIDEC COPAL ELECTRONICS CORP.
1
Characteristics subject to change without notice
Doc. No. MD-2012 Rev. H