SM3-ITG Datasheet, PDF (4/32 Pages) Connor-Winfield Corporation – ULTRA MINIATURE STRATUM 3 MODULE

Figure 2
Pin Diagram
LOS
LOL
M/S REF
REF1
REF2
REF3
REF4
TDI
TMS
TRST
BITS_CLK
M/S_OUT
OUTPUT1
VPP
1
SM3-ITG
28
2
27
3
26
4
25
5
24
6
23
7
22
(TOP VIEW)
8
21
9
20
10
19
11
18
12
17
13
16
14
15
MASTER SELECT
SPI_INT
SPI_OUT
RESET
SPI_ENBL
Vcc
SPI_IN
SPI_CLK
GND
TCK
TDO
HOLD_GOOD
T1/E1
VPN
Register Map
Table 3
Address
0x00
0x01
0x02
0x03
0x04
Reg Name
Chip_ID_Low
Chip_ID_High
Chip_Revision
Bandwidth
Ctl_Mode
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
Op_Mode
Max_Pullin_Range
M/S REF_Activity
Ref_Activity
Ref_Pullin_Sts
Ref_Qualified
Ref_Mask
Ref_Available
Ref_Rev_Delay
Phase_Offset
Description
Type
Low byte of chip ID
R
High byte of chip ID
R
Chip revision number
R
Bandwidth Select
R/W
Manual or automatic selection of Op_Mode,BITS clock output frequency R/W
indication, and frame/multi-frame sync pulse width mode control
Master Free Run, Locked, or Hold Over mode, or Slave mode
R/W
Maximum pull-in range in 0.1 ppm units
R/W
Cross Reference activity
R
Activities of 4 reference inputs
R
In or out of pull-in range of 4 reference inputs
R
Qualification status of 4 reference inputs
R
Availability mask for 4 reference inputs
R/W
Availability of 4 reference inputs
R
Reference reversion delay time, 0 - 255 minutes
R/W
Phase offset between M/S REF & M/S Output (for the Slave in M/S operation)
in 250ps resolution
R/W
SM3-ITG Data Sheet #: TM074 Page 4 of 32 Rev: 05 Date: 09/06/11
© Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice