SCG102A Datasheet, PDF (3/8 Pages) Connor-Winfield Corporation – Synchronous Clock Generators

Table 2
Specifications
Symbol
f_IN
f_OUT
Vcc
I_CC
CLKIN
CLKOUT
V
OH
V_OL
T_R/T_F
SYM
BW
J_GEN
J
TRAN
APR
T_OP
Parameter
Available Input Frequencies CMOS
PECL
Output Frequencies(LVPECL)
Supply Voltage
Supply Current
Input Logic A = CMOS
D = PECL
Output Logic F = Comp. PECL
Rise/Fall Time
Output Symmetry
Bandwidth
Jitter Generation RMS
(12 kHz - 20 MHz)
Jitter Transfer
Input Frequency Tracking
Operating Temperature
F=
C=
Minimum
8k
1M
77.76 M
3.135
2.275
Nominal
3.3
75
CMOS
PECL
PECL
0.5
45
20
0.5
±50
-40
0
Maximum
100 M
100 M
170 M
3.465
100
Units
Hz
Hz
Hz
Volts
mA
1.68
1
55
1
0.1
85
70
V
V
ns
%
Hz
ps
dB
ppm
°C
°C
Notes
1
2
NOTES: 1.0: Only HCMOS and LVHCMOS is supported for input frequencies < 1MHz
2.0: GR-253-CORE, Sec. 5.6.2.1.2
Table 3
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Connection
CLKIN
GND
Lock Detector
VCXO Monitor
----
NC
GND
Enable/Disable
Out
COut
NC
Select A
Select B
NC
GND
V_CC
Description
Input Frequency - The SCG102A AC couples the input , this means that the unit is
capable of handling HCMOS, LVCMOS, PECL, LVPECL input signals.
Ground
Logic “1” indicates that the unit is locked to the input reference
Logic “0” indicates that the reference is lost or out of lock range
Control voltage level for the PECL oscillator (Between 0.3V and 3.0V when locked)
Missing
No connection
Ground
Logic “0” (or no connect) = Output Enabled
Logic “1”
= Output Disabled (Tri-Stated)
Output
Complementary Output
No connection
Input Frequency Select Control Pin. See Table 4.
Input Frequency Select Control Pin. See Table 4.
No connection
Ground
Power supply voltage (3.3 Vdc ± 5%)
Data Sheet #: SG076 Page 3 of 8 Rev: 00 Date: 4/11/07
© Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice