SCG3041 Datasheet, PDF (1/12 Pages) Connor-Winfield Corporation – Synchronous Clock Generators

2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: [phone]
Fax: [phone]
www.conwin.com
SCG3041 Series
Synchronous Clock
Generators
PLL
Bulletin
Page
Revision
Date
Issued By
SG041
1 of 12
P01
4 NOV 02
MBatts
Application
The SCG3041 is designed for use as a
reference input for OC-48 Framers and
SERDES. It generates less than 1 psRMS
jitter over the OC-48 bandwidth.
SCG3041 is well suited for use in line
cards, service termination cards and
similar functions to provide reliable
reference, phase locked, synchronization
for TDM, PDH, SONET, and SDH network
equipment. The SCG3041 provides a jitter
filtered, wander following output signal
synchronized to a superior Stratum or peer
input reference signal.
The SCG3041 differs from SCG3040 by
providing a CMOS output at 77.76 MHz.
Features
• 3.3V High
Precision PLL
• Two Differential
LVPECL Outputs
@ 155.52 MHz
• 19.44 MHz CMOS
Input Reference
• Reference Duty
Cycle Tolerant
• Low Temperature
Reflow Surface
Mounting
• CMOS Output
@ 77.76MHz