FPLD64TEG5 Datasheet, PDF (1/2 Pages) Connor-Winfield Corporation – SURFACE MOUNT 3.3V LVPECL CLOCK

THE CONNOR-WINFIELD CORP.
2111 COMPREHENSIVE DRIVE.
AURORA, IL 60505.
FAX [phone].
PHONE [phone].
WWW.CONWIN.COM
PRODUCT
D AT A
SHEET
CRYSTAL CONTROLLED OSCILLATORS
SURFACE MOUNT 3.3V LVPECL CLOCK
CW 0629
FPLD64TEG5
155.52M
ABSOLU TE MAX IMUM RATING S
PARAMETER
Storage Temperature
Supply Voltage
UNITS
(Vcc)
MINIMUM
-55
-0.5
NOMINAL
-
-
MAXIMUM
125
7.0
UNITS
°C
Vdc
TABLE 1.0
NOTE
OPERATING SPECIFIC ATIONS
PARAMETER
Center Frequency
Total Frequency Tolerance
Operating Temperature Range
Supply Voltage
Supply Current
Jitter (BW=10Hz to 20MHz)
Jitter (BW=12kHz to 20MHz)
(Fo)
(Vcc)
(Icc)
MINIMUM
16.384
-20
-4
3.135
-
-
-
NOMINAL
-
-
3.3
-
-
-
MAXIMUM
200
20
85
3.465
60
5
1
UNITS
MHz
ppm
°C
Vdc
mA
pS RMS
pS RMS
TABLE 2.0
NOTE
1
INPUT CHARACTERISTICS
PARAMETER
Disable Input Voltage (High)
Enable Input Voltage (Low)
(Vih)
(Vil)
LVPECL OUTPUT CHARACTERISTICS
PARAMETER
LOAD
Voltage
(High)
(Voh)
(Low)
(Vol)
Duty Cycle
Rise / Fall Time 20% to 80%
MINIMUM
2.275
-
NOMINAL
-
-
MAXIMUM
-
1.68
UNITS
Vdc
Vdc
TABLE 3.0
NOTE
2
2
MINIMUM
-
2.275
-
45
-
NOMINAL
-
-
-
50
-
MAXIMUM
50
-
1.68
55
1
UNITS
Ohms
Vdc
Vdc
%
nS
TABLE 4.0
NOTE
3
4
PACKAG E CHARACTERISTICS
Package
TABLE 5.0
Non-hermetic package consisting of an FR4 substrate with grounded metal
cover.
PROCESS RECOMMENDATIONS
Soldering Process
Wash
See solder profile page 2.
Ultrasonic cleaning is not recommended.
TABLE 6.0
Notes
1) Includes initial tolerance, deviation over temperature, supply and load variations, shock, vibration and 20 years
aging.
2) When the oscillator is disabled, the true output is in a low state (Vol) and the complementary output is in the high
state (VoH).
3) Output must be terminated into 50 ohms to Vcc – 2V or Thevenin equivalent.
4) Duty Cycle measured at 1.977V
FPLD64TEG5
DESCRIPTION
The Connor-Winfield
FPLD64TEG5 is a fixed
frequency, surface mount
Crystal Controlled Oscillator
(XO) designed for applications
requiring low jitter and a
±20ppm overall frequency
tolerance. Operating at 3.3V
supply voltage, the
FPLD64TEG5 provides
LVPECL Differential Outputs
with a Enable/Disable function.
FEATURES
3.3V OPERATION
LOW JITTER <1pS RMS
OVERALL FREQUENCY TOLERANCE:
±20ppm
TEMPERATURE RANGE: -40 to 85°C
LVPECL DIFFERENTIAL OUTPUTS
ENABLE / DISABLE FUNCTION
SURFACE MOUNT PACKAGE
TAPE AND REEL PACKAGING
RoHS 5/6 COMPLIANT
ORDERING INFORMATION
DATASHEET #: ^Ec241 PAGE 1 OF 2
REV: 00
DATE: ^07/19/06
FPLD64TEG5 - 155.52MHz
CLOCK
SERIES
CENTER
FREQUENCY
Specifications subject to change without notice.
aCopyright 2001 Connor-Winfield all rights reserved.