CX82100 Datasheet, PDF (96/226 Pages) Conexant Systems, Inc – Home Network Processor (HNP)

CX82100 Home Network Processor Data Sheet
6.10
EMC I/O Clock Interface and Timing
The EMC I/O clock interface is illustrated in Figure 6-2.
The EMC I/O timing is illustrated in Figure 6-3.
Figure 6-2. EMC Clocking Interface
CLKGEN
MODULE
BCLK BCLK
scan mux
MCLK _PAD
MCLK
scan mux
Q
MA _PAD
MA
D
HNP
D
asb_sdram
Figure 6-3. EMC I/O Timing
scan mux
MD _PAD
MD
Q
ext_sdram
101545_026
BCLK
MCLK
MD
A
B
MA
ADDR
Notes:
A = tck-q + tdsm + tpo
B = tasu
C = clock skew = tdi + tdsm + tpo
D = ta
E = tsu + tpi + tdsm
F = (clk period / 2) - tdi - tdsm - tpo
C
D
E
DATA
W here:
tck-q = asb_sdram flop clk-q delay
tsu = asb_sdram flop setup time
th = asb_sdram flop hold time
tdsm = HNP scan mux delay
tpo = output pad delay
tpi = input pad delay
tdi = HNP inverter delay
ta = sdram read access time
F
101545_027
6-6
Conexant Proprietary and Confidential Information
101306C