CX25870 Datasheet, PDF (42/291 Pages) Conexant Systems, Inc – Video Encoder with Adaptive Flicker Filtering and HDTV Output

1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.9 Adaptations for Clock-Limited Master Devices
Ideally, the graphics controller or proprietary ASIC, in combination with the
CX25870/871, operates in either master or pseudo-master interface. Occasionally,
using either of the clock master configurations is not possible because the master
device does not have the capabilities of receiving a clock from the encoder nor
can it synchronize the digital data with this clock on its return. If either limitation
exists, only slave interface can be used for the system configuration. Often,
within the slave interface, the data master can only generate certain discrete clock
frequencies. This means the encoder has to make extra accommodations for
normal TV Out to occur.
Fortunately, the encoder does have the flexibility to adapt to almost any
incoming clock frequency in the range from 20 MHz to 80 MHz. All that is
required is to follow the procedure in Table 1-13 which forces the encoder to
accept a frequency through CLKI that does not match any CX25870/871
autoconfiguration frequency. Once the CX25870/871’s 4-byte wide MSC register
is reprogrammed accordingly, the result is the generation of the correct color
subcarrier frequency for NTSC or PAL and corresponding proper S-Video or
Composite TV output.
Table 1-13 and Table 1-14 contain the procedures required for the encoder to
accept a frequency through CLKI that is not equal but is close to the chosen
CX25870/871 autoconfiguration mode clock frequency. Completion of the steps
contained in the two tables will modify the MSC register and PLL_INT and
PLL_FRACT registers correctly and thus produce an accurate NTSC or PAL
analog output.
Table 1-13. Adjustment to the CX25870/871 MSC Registers
1. What is input frequency to CX25870/871’s CLKI input from data master?
2. Depending on answer to step 1, find an autoconfiguration mode that has a frequency close to the
incoming input frequency (within 1 MHz is preferred).
3. Look up the clock frequency for the chosen autoconfiguration mode in Appendix C of the
CX25870/871 data sheet.
4. Determine the scaling factor ‘x’ where
x = input frequency to CLKI input (usually from data master)
autoconfiguration mode frequency as specified in Appendix C
5. Determine the autoconfiguration mode’s MSC[31:0] value in hex by reading back the CX25870/871’s
registers; 0xB4(=MSB), 0xB2, 0xB0, 0xAE(=LSB). These register values can also be found by
looking them up in Register C. The values determined will have to be cascaded together.
6. Convert the MSC[31:0] 4-byte hexadecimal value to decimal.
7. Divide the total found from step 6 by the scaling factor ‘x’ found from step 4.
8. Convert the answer from step 7 to the hexadecimal format. This value should be comprised of a total
of 4 bytes. The most significant byte will likely not change from the previous value in register
MSC[31:24]. Other MSC values may not change either but the least significant bytes should have
definitely been modified.
9. Program the bytes determined from step 8 into the CX25870/871’s MSC[31:0] registers. Write these
bytes in order to registers 0xB4 (most significant byte = MSC[31:24]), 0xB2, 0xB0, and 0xAE (least
significant byte = MSC[7:0]).
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