CPDVR105V0USP-HF Datasheet, PDF (1/4 Pages) Comchip Technology – Low Capacitance ESD Protection Array

Low Capacitance ESD Protection Array
CPDVR105V0USP-HF
RoHS Device
Halogen Free
Features
- IEC61000-4-2 Level 4 ESD Protection.
- IEC61000-4-4 Level 4 FET protection.
- Protects four high speed I/O lines
- Low clamping voltage
- Working Voltage: 5V
- Low leakage current
Mechanical data
- Case: SLP2510P8 small outline plastic package
- Terminals: Matte tin plated, solderable per
MIL-STD-202,method 208
- Mounting Compound Flammability Rating: UL 94V-0
- High temperature soldering guaranteed:
260°C/10 second
- Weight: 0.015 grams(approx.).
Circuit Diagram
12 3 45
SLP2510P8
0.102(2.60)
0.094(2.40)
0.043(1.10)
0.035(0.90)
0.02(0.50)BSC
0.026(0.65)
0.020(0.50)
0.002(0.05)
0.000(0.00)
0.018(0.45)
0.014(0.35)
0.010(0.25)
0.006(0.15)
Dimensions in inches and (millimeter)
10 9 8 7 6
Electrical
Characteristics
(at
TA=25
O
C
unless
otherwise
noted)
Parameter
Reverse working voltage
Breakdown voltage
Reverse Leakage current
Junction capacitance
Junction capacitance
ESD capability
Clamping voltage
Peak pulse power
Junction temperature range
Storage temperature range
Conditions
I/O Pins to GND (Note 1)
IT = 1mA,I/O Pin to GND
VRWM = 5V, I/O Pin to GND
VR =0V, f =1MHz between I/Os
VR =0V, f =1MHz between I/Os GND
IEC 61000-4-2(Air)
IEC 61000-4-2(Contact)
IPP = 1A,I/O Pin to GND(8/20µs)
Tp=8/20µs waveform
Symbol
VRWM
V(BR)
IR
CJ
CJ
VESD
VESD
VC
PPP
TJ
TSTG
Min
6.0
-55
-55
Typ _{Max Unit}
5.0
V
V
1.0
uA
0.4
pF
0.8
pF
±15 kV
±8
kV
15
V
150
W
150
°C
150
°C
Note: 1. ESD devices are normally selected according to the working peak reverse voltage (VRWM), which should
be equal or greater than the DC or continuous peak operating voltage level.
Company reserves the right to improve product design , functions and reliability without notice. REV:A
QW-JP041
Comchip Technology CO., LTD.
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