ACPDVR105V0USP-HF Datasheet, PDF (1/4 Pages) Comchip Technology – Low Capacitance ESD Protection Array

Low Capacitance ESD Protection Array
ACPDVR105V0USP-HF
RoHS Device
Halogen Free
Features
- IEC61000-4-2 Level 4 ESD protection
- IEC61000-4-4 FET 40A ( 5/50ns )
- Protects four high speed I/O lines
- Low clamping voltage
- Working Voltage: 5V
- Low leakage current
- Comply with AEC-Q101
Mechanical data
- Case: SLP2510P8 small outline plastic package
- Terminals: Matte tin plated, solderable per
MIL-STD-202,method 208
- Mounting Compound Flammability Rating: UL 94V-0
- High temperature soldering guaranteed:
260°C/10 second
- Weight: 0.015 grams(approx.).
Circuit Diagram
12 3 45
SLP2510P8
0.102(2.60)
0.094(2.40)
0.043(1.10)
0.035(0.90)
0.02(0.50)BSC
0.026(0.65)
0.020(0.50)
0.002(0.05)
0.000(0.00)
0.018(0.45)
0.014(0.35)
0.010(0.25)
0.006(0.15)
Dimensions in inches and (millimeter)
10 9 8 7 6
Maximum Ratings and Electrical Characteristics (at TA=25°C unless otherwise noted)
Parameter
Conditions
Symbol Min ^Typ Max Unit
Reverse working voltage
I/O Pins to GND (Note 1)
VRWM
5.0
V
Breakdown voltage
IT = 1mA,I/O Pin to GND
V(BR)
6.0
V
Reverse Leakage current
VRWM = 5V, I/O Pin to GND
IR
1.0
uA
Junction capacitance
VR =0V, f =1MHz between I/Os
CJ
0.4
pF
Junction capacitance
ESD capability
Clamping voltage
VR =0V, f =1MHz between I/Os GND
IEC 61000-4-2(Air)
IEC 61000-4-2(Contact)
IPP = 1A,I/O Pin to GND(8/20µs)
CJ
VESD
VESD
VC
0.8
pF
±15 kV
±8
kV
15
V
Peak pulse power
Tp=8/20µs waveform
PPP
150
W
Junction temperature range
TJ
-55
150
°C
Storage temperature range
TSTG
-55
Note: 1. ESD devices are normally selected according to the working peak reverse voltage (VRWM), which should
be equal or greater than the DC or continuous peak operating voltage level.
150
°C
Company reserves the right to improve product design , functions and reliability without notice.
AQW-JP004
Comchip Technology CO., LTD.
REV:A
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