FX614 Datasheet, PDF (9/17 Pages) CML Microcircuits – Optional Line Equalisation

Bell 202 Compatible Modem
FX614
1.5.8 Rx Data Retiming
This function may be used when the received data consists of 1200bits/sec asynchronous characters, each
character consisting of one start bit followed by a minimum of 9 formatted bits as shown in the table below.
Data bits
7
7
8
8
9
Parity bits
0
1
0
1
0
Stop bits
>=2
>=1
>=1
>=1
>=1
The Data Retiming block, when enabled in receive mode, extracts the first 9 bits of each character following
the start bit from the received asynchronous data stream, and presents them to the µC under the control of
strobe pulses applied to the CLK input. The timing of these pulses is not critical and they may easily be
generated by a simple software loop. This facility removes the need for a UART in the µC without incurring an
excessive software overhead.
The receive retiming block consists of two 9-bit shift registers, the input of the first is connected to the output
of the FSK demodulator and the output of the second is connected to the RXD pin. The first register is clocked
by an internally generated signal that stores the 9 received bits following the timing reference of a high to low
transition at the output of the FSK demodulator. When the 9th bit is clocked into the first register these 9 bits
are transferred to the second register, a new stop-start search is initiated and the CLK input is sampled. If the
CLK input is low at this time the RDYN pin is pulled low and the first received bit is output on the RXD pin. The
CLK pin should then be pulsed high 9 times, the first 8 high to low transitions will be used by the device to
clock out the bits in the second register. The RDYN output is cleared the first time the CLK input goes high. At
the end of the 9th pulse the RXD pin will be connected to the FSK demodulator output.
So to use the Data Retiming function, the CLK input should be kept low until the RDYN output goes low; if the
Data Retiming function is not required the CLK input should be kept high at all times.
The only restrictions on the timing of the CLK waveform are those shown in Figure 6a and the need to
complete the transfer of all nine bits into the µC within the time of a complete character at 1200bits/sec.
© 1997 Consumer Microcircuits Limited
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