FX604 Datasheet, PDF (4/17 Pages) Sanyo Semicon Device – Ultrahigh-Speed Switching Applications

V.23 Compatible Modem
FX604
FX604
D4/P3
Signal
Description
Pin No.
Name
Type
9
V_BIAS
O/P Internally generated bias voltage, held at VDD/2
when the device is not in 'Zero-Power' mode.
Should be decoupled to VSS by a capacitor
mounted close to the device pins.
10
RXEQ
I/P A logic level input for enabling/disabling the
equaliser in the receive filter. See section 1.5.4.
11
TXD
I/P A logic level input for either the raw input to the
FSK Modulator or data to be re-timed depending
on the state of the M0, M1 and CLK inputs. See
section 1.5.9.
12
CLK
I/P A logic level input which may be used to clock
data bits in/out of the FSK Data Retiming block.
13
RXD
O/P A logic level output carrying either the raw
output of the FSK Demodulator or re-timed
characters depending on the state of the M0, M1
and CLK inputs. See section 1.5.8.
14
DET
O/P A logic level output of the on-chip energy detect
circuit.
15
RDYN
O/P "Ready for data transfer" output of the on-chip
data retiming circuit. This open-drain active low
output may be used as an Interrupt
Request/Wake-up input to the associated µC.
An external pull-up resistor should be connected
between this output and VDD.
16
V_DD
Power The positive supply rail. Levels and thresholds
within the device are proportional to this voltage.
Should be decoupled to VSS by a capacitor
mounted close to the device pins.
Notes: I/P = Input
O/P = Output
This device is capable of detecting and decoding small amplitude signals. To achieve this V_DD and V_BIAS
decoupling and protecting the receive path from extraneous in-band signals are very important. It is
recommended that the decoupling capacitors are placed so that connections between them and the device
pins are as short as practicable. A ground plane protecting the receive path will help attenuate interfering
signals.
© 1996 Consumer Microcircuits Limited
4
D/604/3