FX631 Datasheet, PDF (2/9 Pages) CML Microcircuits – Low-Voltage SPM Detector

Pin Number
Function
FX631 FX631
D5 DW/P
1
1
Xtal/Clock: The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in
conjunction with the Xtal output (see Figure 2); circuit components are on chip. Using this mode
of clock_2.o₃p_Pe_inra_Fti_uo_nn_c,_tit_oh_ne_DC_el_so_cc_rik_ptO_iou_nt pin should be connected directly to the Clock In pin. If a clock
pulse input is employed to the Clock In pin, this pin must be connected directly to V_DD (see
Figure _X2_T)._{AL The input of the oscillator inverter.}
XTALN The output of the oscillator inverter
4
2 Xtal: The output of the on-chip clock oscillator inverter.
CLKIN The input to the internal clock divider circuitry.
5
3
Clock ^WOu^het:^{n a}A³c^.l⁵o⁷c⁹k⁵⁴s⁵ig^Mn^Ha^zl d^ce^ryr^siv^tae^ld^isfr^uo^sm^edt^,h^ite^so^hon^u-c^ldh^bip^eX^cotaⁿlⁿo^es^cc^teil^dla^ato^crr^o.^sI^sf t^Xh^Te^Ao^Ln^&-c^Xh^Tip^Ao^Ls^acⁿil^dla^Xto^Tr^Ai^Ls
used, t^sh^his^oup^ldin^bs^eh^doⁱu^reld^ctlb^ye^cocⁿoⁿn^en^cn^tee^dct^te^od^Cd^Li^Kre^INc^.tl^Ny^oto^ott^hh^ee^r C^exlo^tec^rk^naIn^{l c}p^oi^mn.^poTⁿh^eis^nto^su^at^rp^euⁿt^es^ch^eo^su^sald^ryn^bo^et^cb^ae^usu^esed
to clock^theot^oh^te^hr^erd^oe^sv^cic^ille^as^to.^{r components (capacitor, resistor) are on chip.}
When an externally available clock signal is used, it should be inserted at CLKIN. XTAL should
be tied to VDD or Vss and XTAL should be left open circuit.
6
4
Clock In: The 3.579545MHz clock pulse input to the internal clock-dividers. If a clock pulse
input is^Se^Ym^STp^Elo^Mye^Ad^l,^ot^gh^ice ⁱX^npta^ul^t/C^pilⁿoc^wk^hii^cn^hp^cu^otⁿ(^tP^roin^ls1^w)^hs^eh^tho^eu^rld^thb^ee^dec^voⁱn^cene^dc^et^te^ecd^tsto¹²V^Kh.^zS^Se^Pe^MF^toigⁿu^er^se⁽2^lo.^{gic 1)}
or 16Khz SPM tones (logic 0). It has an internal 1 Mohm pull- up resistor^D(^Dl 2Khz).
8
7
V_beBIAdSe: _cTaNohmu^Eep_pGo_lliIefPu_ideAt^Trpt_.Mhou^ePtV_Ooⁿ_Sf^eP_S^gt(h^a_se^t_e^ivoe^enFⁱ-ⁿ_icg^ph^u_ui^tpr^,_e^pa2^on^s_)a.^itlⁱo^veguⁱⁿe^pub^tia^as^ndci^orc^uu^tpit^ur^ty^r.^eH^spe^eld^ctiⁱn^vete^lyrn^oa^f l^tl^hy^ea^gt^aVⁱⁿ_DD^a/^d2^j,^ut^sh^tiiⁿs^gp^Pin^Os^Sh^IPould
External components are used in conjunction with the op -amp according to the required level
12
8
V_SS: Nesgenastivtiveitsyuapnpdlyderapeiln(dGinNgDo)n. whether the incoming signal is differential or common mode.
VDD ^TT^hh^ee p^po^ow^se^itr^ivs^eup^apⁿl^dy,ⁿg^ero^gu^an^td^iva^en^sd^igfiⁿlt^aer^{l i}bⁿia^ps^utp^sin^ts^o,re^asⁿp^dec^thtiv^ee^oly^u. ^{tput from, the input gain}
13
9
Signal In (+):_{VSS adjusting signal amplifier. Refer to the graph in Figure 4 for guidance on}
BIAS^sV^eo^ttoⁱⁿa^gnd^leb^vi^ea^ls^ss^ehⁿo^suⁱl^td^ive^ita^iech^s b^toe ⁿd^ae^t-^iocoⁿu^ap^l l^se^pd,^ev^ciⁱa^fica^a1^tio.0ⁿ@^s,F^acⁿa^dpa^thci^eto^sr,^et^lo^ecV^tS^ioSⁿ. ^{of gain}
17 10 Signal In (-): _{adjusting components.}
TTFOP TRUE TONE FOLLOWER OUTPUT. This is the pin that responds and de-
18 11 Amp Out:
responds within 4ms of a good tone appearing or disappearing.
19 13 Tone F^Io^t l^islo^tw^hue^sr^liO^keu^atpⁿu^etⁿ:^vT^eh^loi^ps^eo^ou^ftp^thu^et ^Sp^Pro^Mvi^td^oeⁿs^e.a logic “0” (Low) for the period of a detected tone,
and a logic “1” (High) for NOTONE detection. See Figure 7.
· logic 0 represents ‘detect’ and logic 1 represents ‘not detect’.
20 14 Packet ModeDOTFuOtpPuTth:isAislotghiec oouuttppuut totfhtahet w‘dielllabyeedavtoanileabfolelloawfeter’rbaloccuk.mulation of 40ms of 'good'
tone has been received. This packet mode tone follower will only respond when a tone
frequenItcwyilol rfessupfofincdiewnht eqnu4a0limtyshoafsgbooedentorneecheaivsebdeefonrrseuceffiivceiednwt ithiminea,ni.ye4. 8amcsuwminudlaotwio.nThoef 4408mss iisn
any 48dmivsid, esdhoinrttoto2n4e‘pbauckrsets’ oorf 2bmresaekascwh i(l1l b6Kehizgnmoordeed). oTr h15is‘poauctkpeutts’porof 2v.id66e7smasloeagcich “(01”2K(Lhozw) for
a detecmteodet)o.nEeacahndpaackloetgricep“r1e”se(Hntisgh3)2fcoyrcNleOsToOfNSEPdMetferecqtiuoenn.cSy.eTehFeigwuinrdeo7w. is a shifting window,
ie. the 48ms window is assessed every 2ms (16Khz mode) or 2.667ms (12Khz). If the necessary
number of good packets are consecutive, the output will respond in the minimum time of 40ms.
21 15 System: The logic input to select device operation to either 12kHz (logic “1” - High) or 16kHz
(logic “0” - Low) SPM s_·y_los_gte_icm₀s_r._eT_ph_reis_sein_np_tsu_‘t_dh_eta_es_cta_{’ a}n_ni_dnt_le_or_gn_ica₁l 1_reM_pΩ_resp_eu_nll_tu_sp_‘nr_oe_ts_di_es_tt_eo_cr_t’(_.12kHz).
24 16 V_DD: Positive supply rail. A single, stable power supply is required. Critical levels and voltages
within the FX631 are dependant upon this supply. This pin should be decoupled to V_SS
by a capacitor mounted close to the pin.
Note that if this device is ‘line’ powered, the resulting supply must be stable. See notes on
Microcircuit Protection from high and spurious line voltages.
2, 3, 7, 5, 6,
9, 10, 12
11, 14,
15, 16,
22, 23
No internal connection, leave open circuit.
2