CMX993 Datasheet, PDF(12/26 Page) CML Microcircuits – Programmable 30dB Output Gain Range

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

CMX993 Datasheet, PDF (12/26 Pages) CML Microcircuits – Programmable 30dB Output Gain Range

◁

Quadrature Modulator

CMX993/CMX993W

5.2.2 Filter Amplifiers

A further pair of amplifiers are provided which may be used to implement filtering or buffering. These

uncommitted amplifiers (configured as voltage followers in the case of the CMX993) may be used to

implement Sallen-Key style filters or configured as needed.

The amplifiers are low power and are enabled using the âGeneral Control Registerâ (see section 6.2). It is

not possible to independently control each amplifier, both are enabled with a common control bit.

Note: Input Amplifiers and Filter Amplifiers have independent controls.

5.2.3 CMX993/CMX993W Difference

The essential difference between the CMX993 and the CMX993W is the amplifier stage provided for the

Filter Amplifier. In the CMX993, the Input Amplifier and Filter Amplifier are of a similar design with a gain-

bandwidth product of about 10MHz. To support wider modulation bandwidths the CMX993W uses a high-

speed amplifier for the Filter Amplifier (Note: only the Filter Amplifier is different, the Input Amplifier in the

CMX993W is the same as the Input amplifier in the CMX993.) Because of the extra gain/bandwidth in the

CMX993W a âgain reductionâ mode is provided for the CMX993W Filter Amplifier, see section 6.2.

5.3 Reference Voltages

The CMX993/CMX993W includes on-chip reference voltage generation. Any noise present on the VREF

pin should be decoupled to Analogue Ground (VEE). A buffered version of the reference is provided on the

BVREF pin. After further filtering to remove noise, this may be used to provide the dc reference for

modulator mixer inputs.

5.4 Data Interface

The CMX993/CMX993W is controlled via a three wire C-BUS. A further pin (RESETN) is provided which,

when âlowâ, generates a reset signal (see section 6 for further details). This pin should be pulled to VDDIO

with a suitable resistor (e.g. 100kï) if not used.

The data interface can run at a lower voltage than the rest of the IC by setting VDDIO to the required

interface level in the range 1.6V to 3.6V. Full details of the control register structure are given in section 6.

ï£ 2013 CML Microsystems Plc

D/993/10

▷