CMX910 Datasheet, PDF (1/61 Pages) CML Microcircuits – Flexible Signal Channels

CMX910
AIS Baseband Processor
D/910/6 March 2009
Features:
• Half-Duplex GM(F)SK, FSK and DSC Capabilities
• Slot/Sample Counter with UTC Timing Interface
• Optimum Co-channel and Adjacent-channel
Performance
• Flexible Signal Channels
– Two Simultaneous Rx
– One Tx
– Optional FSK Interface
• AIS Data Formatted and Raw Data Modes
• Supports Carrier-Sensing Channel Access
(CSTDMA) Operation
• RF Device-Enable Facilities
• C-BUS Serial Interface with Expansion Port
Provisional Issue
• I and Q Radio Interface
• Low-Power (3.0 to 3.6V) Operation
• Low Profile, 64-lead LQFP (L9) and
Leadless VQFN (Q1) Packages
• Auxiliary ADC and DAC Functions
– 5 x (10-bit) DACs
– 5-Input MUX (10-bit) ADC
Applications:
• Automatic Identification System
(AIS) for Marine Safety
• Class A or B AIS Transponders
• AIS Rx-only Modules
Radio
Rx1: I/Q
down-
converter
Tx: I/Q
RF _up-
converter
Rx2: I/Q
down-
converter
Optional
FSK
Demod.
(FX604)
Aux
ADC
Aux
DACs
CMX910
Σ−Δ
ADCs
Σ−Δ
DACs
Σ−Δ
ADCs
GMSK/
FSK
decoder
GMSK/
FSK
encoder
GMSK/
FSK
decoder
HDLC/
NRZI
decoder
Message
buffer
HDLC/
NRZI
decoder
Message
buffers
HDLC/
NRZI
encoder
Message
buffers
C-BUS
Interface
C-BUS
Expansion
Port
Device
Enable
Port
FSK
Retiming
(External)
Reset and
Power
Control
Slot and
Sample
Timer
Interrupt
Generator
Host µC
Other
C-BUS
Devices
GNSS
Engine
TCXO
1. Brief Description
A highly integrated Baseband Signalling Processor IC, the CMX910 fulfils the requirements of the class A
and class B marine Automatic Identification System (AIS) transponder market. The CMX910 is half duplex
in operation, comprising two parallel I+Q Rx paths and one Tx path. These are configurable for AIS or
DSC operation. The device performs channel filtering and signal modulation/demodulation with
associated AIS functions, such as training sequence detection, NRZI conversion and HDLC processing
(flags, bit stuffing/de-stuffing, CRC generate/check). An external 1200bps FSK demodulator interface
provides a third parallel decode path for DSC, as required by the class A market. Integrated Rx/Tx data
buffers and a flexible slot/sample timer are also provided, all of which greatly reduce the processing
requirements of the host µC. Provision of a C-BUS expansion port, an RF device enable port and a
number of auxiliary ADCs and DACs further simplifies the system hardware design, reducing the overall
equipment cost and size.
© 2009 CML Microsystems Plc