CMI8738-MX Datasheet, PDF (7/32 Pages) C-Media Electronics – PCI-6CH C3DX series /PCI-Based HRTF 3D Extension Positional Audio Chip

CMI8738
PCI-6CH C3DX series /PCI-Based HRTF 3D Extension Positional Audio Chip
5. Pin Description
5.1 CMI8738/PCI-6CH C3DX Series Chip Function List
Model
CMI8738/PCI-6CH
CMI8738/PCI-6CH-MX
CMI8738/PCI-6CH-LX
SPDIF/ZVport
YES
YES
NO
5.2 Digital Pin Description
Name
XA31-XA0
XINTA
XINTB
XPRST
XCLK33
XGNT
XREQ
XPME
Number
126-128,1-2,5-7,12-16,19-21,3
2-35,38-41,43-44,47-52
117
118
119
120
121
122
123
XIDSEL
9
XFRAME
23
XIRDY
24
XTRDY
25
PIN Type
I/O
O
O
I
I
I
O
O
I
I/O
I/O
I/O
XDEVSEL
26
I/O
XSTOP
29
I/O
XPAR
30
I/O
XCBE3,2,1,0
8,22,31,42
I/O
VDD
Vcore
GND
XIN
XOUT
XGD7-XGD4
4,10,18,27,37,45,124 +3.3V/+5V
54,115
3,11,17,28,36,46,53,116,125
55
56
+3.3V
GND
I
O
97-94
I
XGD3-XGD0
93-90
I/O
Definition
PCI bus address and data lines
Interrupt request , active-low.
Independent Modem interrupt request
(optional; unused)
Reset
PCI bus clock.
Bus master grant, active-low.
Bus master request, tri-state output,
active-low.
Power Management Event pin (optional;
unused)
ID select, active-high.
Cycle frame, active-low.
Initiator ready, active-low. The bus master
device is ready to transmit or receive data
Target ready, active-low. The target device is
ready to transmit or receive data
Device select, active-low. The target device
has decoded the address of the current
transaction as its own chip select range.
Stop transaction, active-low. The target
device request to the master to stop the
current transaction.
Parity. The pin indicates even parity across
XA31-XA9 and XCBE3-0 for both address and
data phases.
Multiplexed command/byte enable. These
pins indicate cycle type during the address
phase of a transaction.
PCI I/O power pin
Core digital circuit power pin
Digital and PCI I/O ground
14.318Mhz crystal, or external clock input
14.318Mhz crystal
Game port switch input pin.
Switch D to switch A
Game port resistor input pin.
RC3 to RC0
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