CM8888 Datasheet, PDF (18/25 Pages) California Micro Devices Corp – CMOS INTEGRATED DTMF TRANCEIVER

Oxygen^TM Express-series CM8888
High-Performance PCI Express Audio Processor
Audio Interface Timing Parameters
Parameter
LRCK propagation delay from BCLK falling edge
SDOUT propagation delay from BCLK falling edge
Symbol Min
Typ
Tdl
5
-
Tdd
5
-
Max
Units
-
ns
-
ns
7.5.2 Control Interface Timing - 3-Wire Mode
Control Interface Timing - 3-Wire Diagram
Note: latch data at XSPI_CEN clock low mode, XSPI_CEN clock can be low or high mode
Test Conditions: DVCC = 3.3V, DGND =0V, TA=+25^oC, SPI clock 160 ns, unless otherwise stated
Control Interface Timing - 3-Wire Parameters
Parameter
XSPI_CLK rising edge to XSPI_CEN rising edge
XSPI_CLK pulse cycle time
XSPI_CLK pulse width low
XSPI_CLK pulse width high
XSPI_DOUT to XSPI_CLK set-up time
XSPI_DOUT to XSPI_CLK hold time
XSPI_CEN rising to SCLK rising
Symbol
Min
Typ
Tscs
120
-
Tscy
160
-
Tscl
80
-
Tsch
80
-
Tdsu
40
-
Tdho
40
-
Tcss
40
-
Max
Units
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
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