CM118B Datasheet, PDF (13/25 Pages) C-Media Electronics – Highly Integrated & Configurable USB Audio Single Chip

CM118B
Highly Integrated & Configurable USB Audio Single Chip
4.3.2 Mode Pin and PWRSEL Pin
PWRSEL pin affects the power configuration of CM118B; together with MODE pin there are four
combinations that are programmable. As show in the table, only speaker mode can switch to self-power
status.
For Speaker and
Headset Modes
PWRSEL
3.3V
GND
3.3V (Speaker)
Self-Powered with 100mA
MODE
Bus Power with 500mA
GND (Headset)
Bus Power with 100mA
Bus Power with 500mA
For Microphone
Mode
PWRSEL
3.3V
GND
MICONLY
3.3V (Microphone)
Bus Power with 100mA
Bus Power with 500mA
4.4 MCU Interface
On MCU serial interface, the CM118B functions as a slave device with bit rate up to 400Kbps (fast mode). MCU
can read/write 3 bytes to the CM118B device with a 2-bit register address. Since host side and MCU can both access
all of the internal registers, access contention should be avoided on application when both try to access the same
register. The7-bit slave address of the CM118B is assigned as 7’b0111000.
When a one-byte data is written by MCU, the CM118B will transfer totally 4 bytes to the USB host via an
additional interrupt pipe. The sequence of the upward HID report is given by: the button status first (address00);
then register with address01; followed by register with address02; lastly, register with address03. The USB host
will keep polling the upward HID report every 2mS. When there is any button pressed or released, or MCU data
coming, the CM118B will transfer the 4 bytes of HID report to the USB host again.
The CM118B can also transfer one byte MCU data from the USB host to its register. This is accomplished by a
‘Set Output Report’ HID class request via default control pipe. MCU can get this downward byte by polling.
The CM118B has one input pin ‘SCLK’ where it gets serial clock from MCU, and one open-drain output pin ‘SDAT’
where it sends or receives serial signal to or from MCU. As shown below, ‘SDAT’ should best able when ‘SCLK’ is high,
and can only have transition when ‘SCLK’ is low.
Datasheet Revision: 1.00
Page 13 / 25
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