CPC7220 Datasheet, PDF (8/11 Pages) Clare, Inc. – Low Charge Injection 8-Channel High Voltage Analog Switch

CPC7220
CPC7220 Description
The CPC7220 takes a serial stream of input data
turns a switch ON.
along with a synchronous clock signal. As the clock
transits from low to high, the data at the input of
Two or more CPC7220 devices can be cascaded to
each shift register is shifted through from SR(n) to
SR(n+1). A high data bit, a "1," represents an ON
switch; a low data bit, a "0," represents an OFF
form an n-switch arrangement. The D_OUT pin of the
first is connected to the D_IN pin of the next in the
series. All devices are connected to the same clock
switch. Data is input and shifted through the internal
(CLK) signal. LE of all devices would normally be
shift register until all eight shift register positions,
connected, as would CL, but this is not necessary.
SR0 through SR7, are in the desired state.
D_IN: The data-in line presents data bits to the
CPC7220 to be shifted through the internal shift
register.
Y _{CLK: The clock signal's rising edge is associated}
R ^{only with shifting data into and through the shift}
register.
CL: The clear line overrides all other inputs. When
A _{CL is high, the shift register is cleared to all 0s}
and all latches are set low, which causes all output
switches to be turned OFF immediately. When CL is
IN ^{low, all output switches remain in whatever state they}
are in, ON or OFF, in response to CLK, latch inputs,
and the LE signal.
IM ^{LE: latch enable controls the state of the latches}
and thus the state of the eight switches. If LE is high,
then the latches do not change states, but retain their
most recent status: either ON or OFF. With LE high,
L _{input data and CLK have no effect on the state of the}
output switches. If LE is low, then all latch outputs
and their switch states follow the inputs from the shift
E _{register. LE is overridden by CL: no matter what state}
LE is in, CL clears the latches. See table on page 10.
R _{DOUT: The data-out pin is the output of SR7. After}
eight clock pulses, the first bit of eight input data bits
P ^{is shifted to SR7 and appears on DOUT.}
The first data bit applied to D_IN of the CPC7220,
whether it's a single device or several cascaded
devices, ripples through to the last switch output in
line after the application of a full clocking sequence
of 8 clock pulses per CPC7220. Setting the serial I/O
device to output the most significant bit (MSB) first,
results in the MSB appearing on SW7 of the last
device in line after a full clocking sequence.
D_IN
CLK
CL
LE
D_IN
CLK
CPC7220
CL
LE
D_OUT
D_IN
CLK
CPC7220
CL
SW0
SW7
SW0
LE
SW0 - SW7: The CPC7220 provides eight high-
voltage SPST output switches with a typical on-
D_OUT
SW7
resistance of 20Ω. The two connections of each
switch are not polarity-sensitive.
V_PP and V_NN: Voltage inputs to the level shifters for
each switch channel that translate the voltage level
D_IN
CLK
SW0
of the latch output signals to an appropriate level for
CPC7220
the voltages being switched.
The high-voltage output switches are turned on and
off in response to the data sent into the latches from
the shift register: data 0 turns a switch OFF, data 1
CL
LE
D_OUT
SW7
8
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