M-986-2R2 Datasheet, PDF (6/13 Pages) Clare, Inc. – MFC Transceivers

M-986-2R2
Signal Description (continued)
Signal
DIP
Pinout
PLCC
Pinout
FR
37
41
FSR
39
43
FSX
38
42
SCLK
34
38
I/O/Z
Description
O
8 kHz internal serial-port framing output. If internal clocking is
selected, serial-port transmit and receive operations occur
simultaneously on an active (high) FR framing pulse.
I
8 kHz external serial-port receive-framing input. If external clocking
is selected, data is received via the receive pins (DR1 and DR0) on
the active (low) FSR input. The falling edge of FSR initiates the
receive process, and the rising edge causes the M-986 to process
the data.
I
8 kHz external serial-port transmit-framing input. If external clocking
is enabled, data is transmitted on the transmit pins (DX1, DX0) on
the active (low) input. The falling edge of FSX initiates the transmit
process,and the rising edge causes the M-986 to internally load data
for the next cycle.
I/O/Z
2.048 MHz serial-port clock. Master clock for transmitting and
receiving serial-port data. Configured as an input in external clocking
mode or output in internal clocking mode. Reset (RS) forces SCLK
to the high-impedance state.
Absolute Maximum Ratings Over Specified
Temperature
Supply voltage range, V_CC
Input voltage range
Output voltage range
Ambient air temperature range
Storage temperature range
-0.3 V to 7 V
-0.3 V to 15 V
-0.3 V to 15 V
0°C to 70°C
-45°C to 150°C
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
Serial Port Timing
Parameter
t_d (CH-FR)
t_d (DX1-CL)
t_d (DX2-CL)
t_h (DX)
t_su (DR)
t_h (DR)
t_c (SCLK)
t_f (SCLK)
t_r (SCLK)
t_w (SCLKL)
t_w (SCLKH)
t_su (FS)
Internal framing delay from SCLK rising edge
DX bit 1 valid before SCLK falling edge
DX bit 2 valid before SCLK falling edge
DX hold time after SCLK falling edge
DR setup time before SCLK falling edge
DR hold time after SCLK falling edge
Serial port clock cycle time
Serial port clock fall time
Serial port clock rise time
Serial port clock low-pulse duration*
Serial port clock high-pulse duration*
FSX/FSR setup time before SCLK falling edge
* The duty cycle of the serial port clock must be within 45% to 55%.
Min
Nom
Max
Units
-
-
70
ns
20
-
-
ns
20
-
-
ns
244
-
-
ns
20
-
-
ns
20
-
-
ns
399
488.28 4770
ns
-
-
30
ns
-
-
30
ns
220
244.14 2500
ns
220
244.14 2500
ns
100
-
-
ns
6
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Rev. 3