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M-986-2A1 Datasheet, PDF (6/13 Pages) Clare, Inc. – MF Transceiver
◁
M-986-2A1
Serial Port Timing
Parameter
td (CH-FR)
td (DX1-CL)
td (DX2-CL)
th (DX)
tsu (DR)
th (DR)
tc (SCLK)
tf (SCLK)
tr (SCLK)
tw (SCLKL)
tw (SCLKH)
tsu (FS)
Internal framing delay from SCLK rising edge
DX bit 1 valid before SCLK falling edge
DX bit 2 valid before SCLK falling edge
DX hold time after SCLK falling edge
DR setup time before SCLK falling edge
DR hold time after SCLK falling edge
Serial port clock cycle time
Serial port clock fall time
Serial port clock rise time
Serial port clock low-pulse duration*
Serial port clock high-pulse duration*
FSX/FSR setup time before SCLK falling edge
* The duty cycle of the serial port clock must be within 45% to 55%.
External Frequency Specifications
tC(MC)
tr(MC)
tf(MC)
Parameter
Master clock cycle time
Rise time master clock input
Pulse duration master clock
Recommended Operating Conditions
Parameter
VCC
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current (all outputs)
IOL
Low-level output current (all outputs)
TA
Operating free-air temperature
All inputs except CLKIN
CLKIN
MC/PM
All inputs except MC/MP
MC/MP
Min
Nom
Max
Unit
-
-
70
ns
20
-
-
ns
20
-
-
ns
244
-
-
ns
20
-
-
ns
20
-
-
ns
399
488.28
4770
ns
-
-
30
ns
-
-
30
ns
220
244.14
2500
ns
220
244.14
2500
ns
100
-
-
ns
Min
48.818
-
20
Nom
48.828
5
-
Max
Unit
48.838
ns
10
ns
-
ns
Min
Nom
Max
Unit
4.75
5
5.25
V
-
0
-
V
2
-
-
V
3
-
-
V
2.2
-
-
V
-
-
0.8
V
-
-
0.6
V
-
-
-300
µA
-
-
2
mA
0
-
70
˚C
6
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Rev. 3
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