CPC7581 Datasheet, PDF (10/12 Pages) Clare, Inc. – Line Card Access Switch

CPC7581
Data Latch
The CPC7581 has an integrated data latch. The latch
operation is controlled by logic level input pin 11
(LATCH). The data input of the latch is pin 10 (INPUT)
and of the device while the output of the data latch is an
internal node used for state control. When LATCH con-
trol pin is at logic 0, the data latch is transparent and data
control signals flow directly through to state control. A
change in input will be reflected in a change is switch
state. When LATCH control pin is at logic 1, the data
latch is now active and a change in input control will not
affect switch state. The switches will remain in the posi-
tion they were in when the LATCH changed from logic 0
to logic 1 and will not respond to changes in input as long
as the latch is at logic 1. In addition, TSD input is not tied
to the data latch. Therefore, TSD is not affected by the
LATCH input and TSD input will override state control via
pin 10 (IN_RING) and the LATCH.
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