MXED401 Datasheet, PDF (1/20 Pages) Clare, Inc. – 200-Column Cholesteric LCD Driver

MXED401
200-Column Cholesteric LCD Driver
FEATURES:
OVERVIEW:
• Drives Reflective-type Liquid Crystal
Clare introduces the MXED401, targeted
Displays
for the emerging non-volatile reflective LCD
• Black-White or Gray-Scale
market, specifically bi-stable and multi-stable
• Cholesteric LCD (ChLCD) Compatible
Cholesteric LCD’s. The MXED401 supports 200
• 200 Output Channels, Cascadeable
phase-controlled voltage data outputs. This is
• 192-Channel Mode
the first standard product driver for ChLCD display
• Token-Based Bi-directional Data
panels.
Transfer
• 6-Bit Data to support 64-Level
Gray-Scale
• ±2V to ±7V panel drive
• 4mA Minimum Source/Sink at ±7VOutput
Levels
• 2.5V to 5V logic supply
• 26 MHz clock frequency
• 4mA Minimum Source/Sink at ±7V Output
Levels
• Gold-Bumped Die @ 60 micron Output Pitch
FUNCTIONAL DESCRIPTION:
The MXED401 driver functions as a level shifter with a resting state at ground potential. Proper
operation of the logic enables gray-scale capability. The output is a 128 Counter Clock (CCLK) event
where each channel is a low resistive switch to external symmetric (with respect to ground) voltage
supplies. Proper operation of the logic allows gray scale capability. The output is initially low (MV4)
from one to sixty-four CCLK times, then continuously high (PV4) for sixty-four CCLK times, returning
low for the balance of the 128 CCLK cycle (before returning to its quiescent value (VSS2)). The data
driver chip is manufactured in a high voltage (30 V) CMOS process and is available in gold-bumped-
die form.
The Token Bit Shift Register is used to control data latch timing for the Temporary Storage Register.
A token bit (initialized by SRIN input) is transferred sequentially among the 200 possible (internal)
outputs of the Shift register. This allows data to fill the Temporary Storage Register to in a Right to
Left fashion. When the Temporary Register is filled its contents may be transferred to the Output
Storage register via the LAT input. Output phase control is then accomplished by the Pulse Phase
Shift Logic, data then passes to the High Voltage Translator unit to control the three output switches
associated with each column output driver.
14580
www.clare.com
January 29, 2003