WM8950 Datasheet, PDF (9/60 Pages) Wolfson Microelectronics plc – ADC WITH MICROPHONE INPUT AND PROGRAMMABLE DIGITAL FILTERS

AUDIO INTERFACE TIMING – SLAVE MODE
BCLK
t_BCH
t_BCL
t_BCY
FRAME
ADCDAT
t_LRH
t_DD
WM8950
t_LRSU
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T_A=+25^oC, Slave Mode, fs=48kHz, MCLK= 256fs,
24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCLK cycle time
t_BCY
BCLK pulse width high
t_BCH
BCLK pulse width low
t_BCL
FRAME set-up time to BCLK rising edge
t_LRSU
FRAME hold time from BCLK rising edge
t_LRH
ADCDAT propagation delay from BCLK falling edge
t_DD
Note: BCLK period should always be greater than or equal to MCLK period.
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
20
ns
Rev 4.5
9