CS5460A Datasheet, PDF (9/54 Pages) Cirrus Logic – Single Phase Bi-Directional Power/Energy IC

CS5460A
SWITCHING CHARACTERISTICS
(T_A = -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels:
Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50 pF))
Parameter
Symbol Min Typ Max Unit
Master Clock FrequencyCrystal/Internal Gate Oscillator (Note 24) MCLK
2.5 4.096 20 MHz
Master Clock Duty Cycle
40
-
60
%
CPUCLK Duty Cycle
(Note 25)
40
60
%
Rise Times
Any Digital Input Except SCLK (Note 26) t_rise
SCLK
Any Digital Output
-
-
1.0
µs
-
-
100 µs
-
50
-
ns
Fall Times
Any Digital Input Except SCLK (Note 26) t_fall
SCLK
Any Digital Output
-
-
1.0
µs
-
-
100 µs
-
50
-
ns
Start-up
Oscillator Start-Up Time
XTAL = 4.096 MHz (Note 27) t_ost
-
60
-
ms
Serial Port Timing
Serial Clock Frequency
SCLK
-
-
2
MHz
Serial Clock
Pulse Width High
t₁
Pulse Width Low
t₂
200
-
200
-
-
ns
-
ns
SDI Timing
CS Falling to SCLK Rising
t₃
50
-
-
ns
Data Set-up Time Prior to SCLK Rising
t₄
50
-
-
ns
Data Hold Time After SCLK Rising
t₅
100
-
-
ns
SCLK Falling Prior to CS Disable
t₆
100
-
-
ns
SDO Timing
CS Falling to SDI Driving
t₇
-
20
50
ns
SCLK Falling to New Data Bit
t₈
-
20
50
ns
CS Rising to SDO Hi-Z
t₉
-
20
50
ns
Auto-Boot Timing
Serial Clock
Pulse Width High t₁₀
Pulse Width Low
t₁₁
8
MCLK
8
MCLK
MODE setup time to RESET Rising
t₁₂
50
ns
RESET rising to CS falling
t₁₃
48
MCLK
CS falling to SCLK rising
t₁₄
100
8
MCLK
SCLK falling to CS rising
t₁₅
16
MCLK
CS rising to driving MODE low (to end auto-boot sequence).
t₁₆
50
ns
SDO guaranteed setup time to SCLK rising
t₁₇
100
ns
Notes: 24. Device parameters are specified with a 4.096 MHz clock, yet, clocks between 3 MHz to 20 MHz can be
used. However, for input frequencies over 5 MHz, an external oscillator must be used.
25. If external MCLK is used, then duty cycle must be between 45% and 55% to maintain this specification.
26. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
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