CS4344 Datasheet, PDF (9/23 Pages) Cirrus Logic – 10-PIN, 24-BIT, 192KHz STEREO D/A CONVERTER

CS4344/5/6/8
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
Parameters
Symbol
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate All MCLK/LRCK ratios combined Fs
(Note 11)
256x, 384x, 1024x
256x, 384x
512x, 768x
1152x
128x, 192x
64x, 96x
128x, 192x
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Duty Cycle
t_sclkl
t_sclkh
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Internal SCLK Mode
t_slrd
t_slrs
t_sdlrs
t_sdh
LRCK Duty Cycle (Internal SCLK only) (Note 12)
SCLK Period
(Note 13) t_sclkw
SCLK rising to LRCK edge
t_sclkr
Min
0.512
45
2
2
84
42
30
50
100
168
45
20
20
45
20
20
20
20
-
----¹---⁰----⁹-----
SCLK
-
SDIN valid to SCLK rising setup time
t_sdlrs
SCLK rising to SDIN hold time
t_sdh
MCLK / LRCK =1152, 1024, 512, 256, 128, or 64
-------1---0----⁹------- + 10
( 512 ) F s
-------1---0----⁹------- + 15
( 512 ) F s
Typ
-
-
50
-
-
50
-
-
-
-
50
-
t---s---c----l-k----w---
2
-
-
SCLK rising to SDIN hold time
t_sdh
MCLK / LRCK = 768, 384, 192, or 96
(^{---3---8-1---40---})^{-9--F----s- + 15}
-
Max
50
55
200
50
134
67
34
100
200
200
55
-
-
55
-
-
-
-
-
-
-
-
-
-
Units
MHz
%
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
%
ns
ns
%
ns
ns
ns
ns
%
ns
µs
ns
ns
ns
Notes: 11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on
page 12 for supported ratio’s and frequencies.
12. In Internal SCLK Mode, the Duty Cycle must be 50% +/− 1/2 MCLK Period.
13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on part type and
MCLK/LRCK ratio. (See figures 7-9)
DS613PP2
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