CS1500 Datasheet, PDF (9/22 Pages) Cirrus Logic – Digital Power Factor Correction IC

May ?$shortyear>
CONFIDENTIAL
CS1500
P_o
[W]
Burst Threshold
Resistor R_FB (shown as R2a & R2b in Figure 21) sets the
feedback current and is calculated as follows:
R_FB
=
V_{-----l-i--n--k----–-----}V_----d---d-
I_ref
[Eq.3]
Burst Mode
Active
t [ms]
V_in
[V]
V_in
PFC
Disable
FET
V_gs
V_link
I_FB
R_FB
VDD
7
t [ms]
Figure 14. Burst Modes
3.4 Output Power and PFC Boost Inductor
Maximum output power in normal mode is defined by the
following equation:
P_o
=
α
×
η
×
(V_in(min))²
×
-^V----^l-ⁱ--ⁿ--^k----–-----⁽--^V----ⁱ--ⁿ---⁽--^m----ⁱ-ⁿ---⁾---^×---------²----⁾-
2 × f_max × L_B× V_link
[Eq.1]
where, V_in(min), V_link, and L_B are user defined based on
application requirements and maximum operating switching
frequency f_max = 70kHz. α is a margin factor to guarantee
rated power (P_o) against tolerances and transients. α is
typically set to 0.9.
The PFC Boost Inductor (LB in Figure 21) value can be
calculated using Equation 1 as follows:
L_B
=
α
×
η
×
(V_in(min))²
×
V_{-----l-i--n--k----–-----}(_--V_{----i--n---(--m----i-n---)---}×_---------2_----)_-
2 × f_max × P_o × V_link
[Eq.2]
where V_in(min) is volts RMS, V_link is volts DC, and α is set to
0.9.
3.5 PFC Output Capacitor
The value of the PFC output capacitor should be chosen
based upon voltage ripple and hold-up requirements. This is
described in more detail in the application section 4.1.6 PFC
Output Capacitor on page 13. To ensure system stability with
the digital controller, the recommended value of the capacitor
is within the range of 0.5 μF / watt to 2.0 μF / watt.
3.6 Output Feedback & Regulation
A current proportional to the PFC output voltage, V_link, is
supplied to the IC on pin FB and is used as a feedback control
signal. This current is compared against a fixed-value internal
reference current, I_ref.
FB
4
ADC
Figure 15. Feedback Input Pin Model
The ADC is used to measure the magnitude of the I_FB current
through resistor R_FB. The magnitude of the I_FB current is then
compared to an internal reference current, I_ref.
By using digital loop compensation, the voltage feedback
signal does not require an external compensation network.
It is recommended that a ceramic capacitor of up to 2.2 nF be
placed between the FB pin and the VDD pin to filter noise in
the layout.
3.7 IAC Signal
V_rect
I_AC
R_AC
VDD
7
IAC
3
ADC
Figure 16. IAC Input Pin Model
A current proportional to the AC input voltage is supplied to the
IC on pin IAC and is used by the PFC control algorithm.
Resistor R_AC (shown as R1a & R1b in Figure 21) sets the IAC
current and is calculated as follows:
R_AC = R_FB
[Eq.4]
For optimal performance, resistor R_AC, R_FB should use less
than 1% tolerance resistor. Resistors can be separated in two
DS849A5
9