CS4525_07 Datasheet, PDF (89/98 Pages) Cirrus Logic – 30 W Digital Audio Amplifier with Integrated ADC

CS4525
9.19.5 Power Down (PDnAll)
Default = 1
Function:
The CS4525 will enter a power-down state when this function is enabled:
1. The power PWM outputs will be held in a high-impedance state.
2. The logic-level PWM outputs will continuously drive a logic ‘0’ if the HiZPSig bit is set and will be held
in a high-impedance state if the HiZPSig bit is clear.
3. AUX_SDOUT, the auxiliary serial data output, will be driven to a digital-low. AUX_LRCK and
AUX_SCLK, the auxiliary serial output’s clocks, will continue to operate if the EnAuxPort bit is set,
ADC/SP is cleared, and the serial audio input receives a valid SCLK and LRCK; otherwise they will
also be driven to a digital-low voltage.
4. DLY_SDOUT, the delay serial data output, will output the unprocessed audio data from SDATA if
EnAuxPort is set, DlyPortCfg[1:0] is configured for serial output delay interface, ADC/SP is cleared,
and the serial audio input port receives a valid SCLK, LRCK, and SDATA. Otherwise, it will drive a
low voltage.
The contents of the control registers are retained in this state. Once the PDnAll bit is disabled, the pow-
ered and logic-level PWM outputs will first perform a click-free start-up function and then resume normal
operation.
The PDnAll bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur.
PDnAll Setting
Device Power-Down State
0 ..........................................Normal device operation.
1 ..........................................Device power-down enabled.
9.20 Interrupt (Address 60h)
7
SRCLock
6
ADCOvfl
5
ChOvfl
4
AmpErr
3
2
1
SRCStateM ADCOvflM ChOvflM
0
AmpErrM
Bits [7:4] in this register are read only. A ‘1’b in these bit positions indicates that the associated condition has oc-
curred at least once since the register was last read. A ‘0’b indicates that the associated condition has not occurred
since the last reading of the register. Reading the register resets bits to [7:4] ‘0’b. These bits are considered “edge-
triggered” events. The operation of these 4 bits is not affected by the interrupt mask bits and the condition of each
bit can be polled instead of generating an interrupt as required.
9.20.1 SRC Lock State Transition Interrupt (SRCLock)
Function:
This bit is read only. When set, indicates that the SRC has transitioned from an unlock to lock state or
from a lock state to an unlock state since the last read of this register. Conditions which cause the SRC
to transition states, such as loss of LRCK, SCLK, an LRCK ratio change, or the SRC achieving lock, will
cause this bit to be set. This interrupt bit is an edge-triggered event and will be cleared following a read
of this register.
If this bit is set, indicating a SRC state change condition, and the SRCLockM bit is set, the INT pin will go
active. To determine the current lock state of the SRC, read the SRCLockSt bit in the interrupt status reg-
ister.
SRCLock Setting
SRC Lock State Change Status
0 ..........................................SRC lock state unchanged since last read of this register.
1 ..........................................SRC lock state changed since last read of this register.
DS726PP1
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