CS42528 Datasheet, PDF (80/91 Pages) Cirrus Logic – 114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

CS42528
12. APPENDIX C: PLL FILTER
The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update infor-
mation to the PLL. This results in the PLL being immune to data dependent jitter effects because the
S/PDIF preambles do not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component chang-
es. The nominal center sample rate is the sample rate that the PLL first locks onto upon application of an
S/PDIF data stream.
INPUT
Phase
Comparator
and Charge Pump
RFILT
CFILT
VCO
CRIP
RMCK
÷N
Figure 27. PLL Block Diagram
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DS586PP5