CS4362 Datasheet, PDF (8/40 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Channel D/A Converter

CS4362
SWITCHING CHARACTERISTICS (For KQ T_A = -10 to +70 °C; For BQ T_A = -40 to +85 °C; VLS =
1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, C_L = 30pF)
Parameters
MCLK Frequency
Symbol
Min
Typ
Max
Units
(Note 16)
Single Speed Mode
Double Speed Mode
1.024
-
6.400
-
51.2
MHz
51.2
MHz
Quad Speed Mode
6.400
-
51.2
MHz
MCLK Duty Cycle
40
50
60
%
Input Sample Rate
LRCK Duty Cycle
Single Speed Mode Fs
4
-
50
kHz
Double Speed Mode Fs
50
-
100
kHz
Quad Speed Mode Fs
100
-
200
kHz
45
50
55
%
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
t_sclkl
20
-
t_sclkh
20
-
t_sclkw
--------²---------
-
MCLK
-
ns
-
ns
-
ns
(Note 17) t_sclkw
--------⁴---------
-
MCLK
-
ns
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
LRCK1 to LRCK2 frequency ratio
(Note 18)
t_slrd
t_slrs
t_sdlrs
t_sdh
20
20
20
20
0.25
-
-
-
-
1.00
-
ns
-
ns
-
ns
-
ns
4.00
Notes: 16. See Table 5 on page 26 for suggested MCLK frequencies
17. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
18. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK
.
LRCK
t _slrd
t _slrs
t _sclkh
t _sclkl
SCLK
t _{sd lrs}
t _{sd h}
SDATA
Figure 1. Serial Mode Input Timing
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