CS4399 Datasheet, PDF (74/111 Pages) Cirrus Logic – 130-dB, 32-Bit High-Performance DAC

CS4399
7.1 Global Registers
Bits
Name
1:0 MCLK_SRC_ Select the source of internal MCLK.
SEL
00 Direct MCLK/XTAL Mode
01 PLL Mode
10 (Default) RCO Mode
11 Reserved
Description
7.1.6 Serial Port Sample Rate
Address 0x1000B
R/W
7
6
5
4
3
2
1
0
—
ASP_SPRATE
Default
0
0
0
0
0
0
0
1
Bits
Name
Description
7:4
—
Reserved
3:0 ASP_SPRATE ASP sample rate. This register must be programmed for both Master Mode and Slave Mode operation.
0000 32 kHz
0001 (Default) 44.1 kHz
0010 48 kHz
0011 88.2 kHz
0100 96 kHz
0101 176.4 kHz
0110 192 kHz
0111 352.8 kHz
1000 384 kHz
1001–1111 Reserved
7.1.7
R/W
Default
Serial Port Sample Bit Size
7
6
5
—
0
0
0
Bits
Name
7:4
—
Reserved
3:2 XSP_SPSIZE XSP sample bit size.
00 32 bits
01 (Default) 24 bits
10–11 Reserved
1:0 ASP_SPSIZE ASP sample bit size.
00 32 bits
01 (Default) 24 bits
10 16 bits
11 8 bits
4
3
2
XSP_SPSIZE
0
0
1
Description
Address 0x1000C
1
0
ASP_SPSIZE
0
1
7.1.8 Pad Interface Configuration
Address 0x1000D
R/W
7
6
5
4
3
2
1
0
—
XSP_3ST
ASP_3ST
Default
0
0
0
0
0
0
1
1
Bits
Name
Description
7:2
—
Reserved
1 XSP_3ST Determines the state of the XSP clock drivers when in Master Mode. When in Slave Mode, the serial port clocks are
inputs, whose function is not affected by this bit. Before setting an xSP_3ST bit, the associated serial port must be
powered down and not powered up until the xSP_3ST bit is cleared.
0 When in Master Mode, serial port clocks are active.
1 (Default) When in Master Mode, serial port clocks are Hi-Z.
0 ASP_3ST Determines the state of the ASP clock drivers when in Master Mode. When in Slave Mode, the serial port clock pins are
inputs, whose function is not affected by this bit. Before setting an xSP_3ST bit, the associated serial port must be
powered down and not powered up until the xSP_3ST bit is cleared.
0 When in Master Mode, serial port clocks are active.
1 (Default) When in Master Mode, serial port clocks are Hi-Z.
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DS1113F1